who has some suggestions on DFT of multi_core processor ?

[lixiangku]

I have no idea about that, someone can give me some advices or paper?
thank you very much!

 

[satyakumar]

Re: who has some suggestions on DFT of multi_core processo

Hi,
Can you tell me which kind of multi processor, or elaborate the question you asked.

 

[Thinkie]

You can DFT is as if it was not multicore, or if the two cores don't communicate with each other set a select bit somewhere and test each one seperately...

if you tell us more details, we can help you more..

 

[lixiangku]

Re: who has some suggestions on DFT of multi_core processo

I will do some DFT of multi_core in several months, so now I only want to find some examples to increase my confidences about that.
I want to ask a question: if there r 16cores in a processor chip, and they are the same with each other. And the pin's numbers of the chip is almost equal to the single core chip. Thus,
(1) for every core's MBIST, control singals: how to translate them?
(2) In order to reduce the test time, I hope the 16 cores are best to test simultaneously, but how to input the patterns and output the responses?
(3) what's more, if we will use the 65ns technics, what types of test should I pay more attentions to? at-speed, delay path? is the IDDQ test useful as well?

so, I feel very confused about the project so far. any suggestion of yours will give me some confidences. thanks a lot!!

 

[Thinkie]

If you have 16 identical core with no interconnections between them that can be wrapped, it is technically feasible to enter the exact same serial scan data in the scan-in inputs and then merge the output signals.

if something goes wrong it will be difficult to tell where is there problem.

Also, you may want to investigate with ATPG pattern compression, a technique in latest Synopsys tools where from a few scan inputs you generate multiple internal scan chains that can help you reduce the time on the tester with minimal overhead in terms of additional logic.