Who can tell me how to build a library cell?

[anwayy]

nanosim block delay calculator (bdc)

I want to build a Clock-gating Cell from TSMC 0.25um standard cell library.
Who can tell me how to build a library cell? Tell me the design flow and tools needed please.
It's a very simple cell consists of only a Latch, a 'and' gate and a 'or' gate. We can build the layout by instance of standard cells from the library, but how to analyze the timing? More importand, how to generate the lib files such as .lib, .sdb, .pdb, .def, .tlf etc. for Logic-synthesis and AP&R tools?
So kind for you to tell me or give me some suggestions! Send me a email please if convenient.

best regards
Jason
zhangyongxin@seu.edu.cn

 

[avin11]

What you want to do is that you want to use library cells to build a bigger system. Well isince you have a library, you can either manually route your design in layout level or you can place and route. To place and route you need to first draw schematic design and export its spice netlist. this is then read ny a place and route tools to automatically route your design using the cells in the library specified. Schematic tools are like S-Edit by Tanner and Layout Editors that also have Place & Route tools are like Tanner L-Edit. Other tools may have separate Place & Route and Editor tools. Hope it was helpful.

By the way, is this a full standard cell library by TSMS?

 

[anwayy]

Thank you.
Yes. I want to use the library cell in a bigger system. I need it to be one of the standard cells.
Since the cell is simple, I considered routing the design manually in layout level.
But I don't know how to generate the .lib files etc. in succession.
As for the TSMC standard cell library, yes, it's a full 0.25um CMOS library of them. But it doesn't include a clock-gating cells.
Do you, or anyone else, know whether TSMC/or any other Foundry supply the cell for their customers?

 

[andy2000a]

How to character std cell ??

as I know TSMC/UMC use some tool can simulation all device corner model & W/L ... create a huge database .. then select best W/L size
.. If no thi s tool , If I want to use hspice simulation a standard cell , which "item" will be measure by hspice ? like measure rise/fall time
delay ... who can provider a hspice command about it .

by the way , How to make a Synopsys library ?? like sdb db file , someone said need library compiler .... have any document for it ..

thank you

 

[anwayy]

"To generate complete .lib you would need the library generation tools like Liberty. In fact set of scripts and utilities which generate the SPICE stimuli for each library cell, control the SPICE runs, collecting the results and translating them into the 3D tables used in .lib".
Something like this, I'm now trying to generate the timing model with synopsys's PathMill.
Two modes are supported, say dynamic mode and static mode. Because the cell contains a latch, i adopt the dynamic mode, extract timing imformation using the BDC(Block Delay Calculation) feature of Nanosim via simulation, and then generate timing model with PathMill.
Also there's a static mode, we can generate timing model directly with PathMill without simulation. So now i need to confirm whether the model is accurate. Anyone have the same experence?
Anyway, it's troublesome to create a full timing model, but if we can do so i thing it's the most safe solution.

 

[anwayy]

I'm just about finishing the cell now. Timing information has been extracted for the .lib file and then compiled in Library Compiler to .db file. The LEF file has also been extracted from the layout and then i got the .plib/.pdb file. Tomorrow i'll generate the verilog simulation model and the .tlf file for Silicon Ensemble P&R from the .lib file.

Now i have a question, do you know how to describe the function for the cell in the .lib file. Can we do it? Because it contains a latch but not output from it directly, it output from the AND2 gate followed. I got the warning message below.
Warning: Line 164828, Cell(CGLPCX1): The function cannot be recognized during functional optimization by Design Compiler.