Can any one teach me, or show me some documents, to learn how to extract on chip capacitor model....and also the Q factor ...
(ex, if I have a measured S parameter form on chip capacitor...how can I use this to extract all the equivilent circuits?!)
I have tried that....
but...actually...I am trying to model a capacitor for silicon base...
(under CMOS process)...
so I am not sure if this will work or not~~~
(the TFC model seems didn't need me to give it any CMOS parameters...)
The TFC model is suited for integrated parallel plate capacitor. If it's not your case you have to go for some custom lumped element model you can find in IEEE - MTTS (for example).
I have seen IC designers use @nsoft H~F~S~S to model
IC inductors and Caps, then port them in to C@DENCE
they seemed to get good correlation between the models
and the IC. I believe the Used TMSC in and it was in
CMOS or BiCMOS. You might want to find any IC Fab
house and see if they have any guide lines or libraries.
I suggest for your application using Momentum to simulate the
actual capacitor geometry you are using. You can import your gdsII file directly into the ADS layout to do this. If you define your silicon substrate losses correctly and also the process layers then you will get a very accurate result. I simulate complete MMICs this way with excellent agreement with measurement up to w-band.
You need something much more complex than just the S-parameters. You can get pretty accurate results in A/N/S/O/F/T E/N/S/E/M/B/L/E or A/D/S M/O/M/E/N/T/U/M since this problem is handled in 2.5D EM simulators okay. Or H/F/S/S if you want a real 3D answer but this is not really necessary. It depends on what software you have to use.
Measure a fixture with a 50 ohm line and a small gap or the capacitor...
Measure the fixture with the chip capacitor solder on it..
Assuming symmetry of the fixture, de-embed the Y-parameters of the chip capacitor from the overall measured Y-parameters.