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Who can help me ? thank for you help!!!

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how to code a verilog program to obtain remainder , but it must be synthesized using Design Compiler?
for examle : a 16-bit data divide 150 ?
thanks !!!!
 

I believe the two codes in this link will help you:
**broken link removed**
 

you may descript it with the behavial such as:
Data[15:0]%150;
 

you may descript it with the behavial such as:
Data[15:0]%150;
It may be not synthesize using the DC?

thank you !
 

It is behavial description, May synthesize by DC, If had the good DesignWare resourcde, you may get to the better result
 

HI
I try to download the code, but i can't do it.
thanks
 

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