who can help me?how to design one bidirection 1/8 multiplexr

module bi_mux_8_1(/*AUTOARG*/
   // Inouts
   Row, Col, 
   // Inputs
   Dir, Sel
   );
   input Dir;
   input [2 : 0] Sel;
   inout         Row;
   inout [7 : 0] Col;
   reg [7:0]   decoded;
   
   // input from row to col
   assign      Col[0] = decoded[0] & Dir ? Row : 1'bz;
   assign      Col[1] = decoded[1] & Dir ? Row : 1'bz;
   assign      Col[2] = decoded[2] & Dir ? Row : 1'bz;
   assign      Col[3] = decoded[3] & Dir ? Row : 1'bz;
   assign      Col[4] = decoded[4] & Dir ? Row : 1'bz;
   assign      Col[5] = decoded[5] & Dir ? Row : 1'bz;
   assign      Col[6] = decoded[6] & Dir ? Row : 1'bz;
   assign      Col[7] = decoded[7] & Dir ? Row : 1'bz;
   // input from col to row
   assign Row = decoded[0] & ~Dir ? Col[0] : 1'bz;
   assign Row = decoded[1] & ~Dir ? Col[1] : 1'bz;
   assign Row = decoded[2] & ~Dir ? Col[2] : 1'bz;
   assign Row = decoded[3] & ~Dir ? Col[3] : 1'bz;
   assign Row = decoded[4] & ~Dir ? Col[4] : 1'bz;
   assign Row = decoded[5] & ~Dir ? Col[5] : 1'bz;
   assign Row = decoded[6] & ~Dir ? Col[6] : 1'bz;
   assign Row = decoded[7] & ~Dir ? Col[7] : 1'bz;
   
   always @(/*AS*/Dir or Sel) begin
      decoded = 8'b00000000;
      decoded[Sel] = 1'b1;
   end
   
endmodule // bi_mux_8_1

   
module test();
   reg                  Dir;                    // To bi_mux_8_1 of bi_mux_8_1.v
   reg [2:0]            Sel;                    // To bi_mux_8_1 of bi_mux_8_1.v

   wire [7:0]           Col;                    // To/From bi_mux_8_1 of bi_mux_8_1.v
   wire                 Row;                    // To/From bi_mux_8_1 of bi_mux_8_1.v

   reg [7:0]           Col_reg;                    // To/From bi_mux_8_1 of bi_mux_8_1.v
   reg                 Row_reg;                    // To/From bi_mux_8_1 of bi_mux_8_1.v

   assign      Col = Col_reg;
   assign      Row = Row_reg;
   
   bi_mux_8_1 bi_mux_8_1(/*AUTOINST*/
                         // Inouts
                         .Row           (Row),
                         .Col           (Col[7:0]),
                         // Inputs
                         .Dir           (Dir),
                         .Sel           (Sel[2:0]));
   initial begin
      $monitor ($time,,"Dir = %b Sel = %b Col = %b Row = %b ", Dir, Sel, Col, Row);
      Dir = 1;
      Col_reg = 8'bzzzzzzzz; 
      Row_reg = 1'b1; 
      Sel = 0;
      #10 Sel = 1;
      #10 Sel = 2;
      #10 Sel = 3;
      #10 Sel = 4;
      #10 Sel = 5;
      #10 Sel = 6;
      #10 Sel = 7;
      #10;
      
      Dir = 0;
      Col_reg = 8'b10101010; 
      Row_reg = 1'bz; 
      Sel = 0;
      #10 Sel = 1;
      #10 Sel = 2;
      #10 Sel = 3;
      #10 Sel = 4;
      #10 Sel = 5;
      #10 Sel = 6;
      #10 Sel = 7;
      #10 $finish;
   end
   
endmodule // test

module top (Dir, Sel, Row, Col);
  input        Dir;  // Low selects row-to-col. High selects col-to-row.
  input  [2:0] Sel;
  inout        Row;
  inout  [7:0] Col;

  assign Row = Dir ? Col[Sel] : 'bz;
  assign Col = Dir ? 'bz : {7'bz,Row,7'bz} >> (7-Sel);
endmodule

module top (Dir, Sel, Row, Col);
  input  [7:0] Dir;  // Low selects row-to-col. High selects col-to-row.
  input [23:0] Sel;  // Eight 3-bit selectors
  inout  [7:0] Row;
  inout  [7:0] Col;

  genvar n;
  generate
    for (n=0; n<8; n=n+1) begin : muxs
      assign Row[n] = Dir[n] ? Col[Sel[n*3+2:n*3]] : 'bz;
      assign Col[n] = Dir[n] ? 'bz : Row[Sel[n*3+2:n*3]];
    end
  endgenerate
endmodule