[SOLVED] Who can explain blind vias ,bured vias , microvias ,through hole

[greatmarx]

What is the via hole diameter,internal pad diameter?Does the via hole diameter contain the cu of the via?Does the via filled with cu or microvias is filled with cu?
Does the diameter of via is the same between the outer layer and the inner layer?
regard
Yang

 

[FvM]

The answer to many of your questions depends on the particular technology used by a PCB manufacturer and the respective design rules. There's no general answer. You may want to consult manufacturer imformations for details. Some points can be said in general:

- It's usual to specify the finished viad diameter, the same as you do for through plated component pads. That means, the drill tool used by the manufacturer is 100 or 150 µm larger.
- Below a certain nominal diameter, vias can't be guaranteed to have an open hole. On the other hand, it's not possible to fill a via completely with copper during the galvanic process. But in some technologies small vias can be assumed sufficiently filled, that you are able to place them on SMD pads without further treatment. Larger vias may be "plugged", that means filled, grinded and covered with copper.

 

[marce]

This will cover microvias
Book Download Form

For the rest I would strongly reccomend you get hold of the following:
IPC-2221 to IPC-2226

 

[greatmarx]

I googled that IPC-4761 is about vias,how can I get the IPC-4761.

 

[marce]

IPC-4761 is about the protection of vias, not a description of via types. You have to buy the IPC specs, and for general PCB design guidlines it is the IPC-222x series.
This link shows blind, burried and normal.
**broken link removed**)

 

[greatmarx]

I want to know the detail of vias,not the sample difference.
I tried to simulate the parameters of vias by using Saturn PCB Design,but I can't fill the parameter.
For example ,the bind via on the pcb using the circle of 0.1mm inner and 0.3mm outer from layer1 to layer2 in our company.
And I know the oz of layer1 and layer2.
How to simulate the via?
regard
yang.

 

[marce]

Generaly you will get 0.020-0.025mm plating down the via barrel. Via height is approx same as your PCB, about 1.6mm for standard boards, for blind vias it is the same as the layer stack distance the via covers (ie distance between internal copper layers) For a micrvia from layer 1 to 2 its approx 0.1mm. Via finished hole diameter is 0.1mm.

 

[greatmarx]

How can I use the 0.3mm?It is uselessfully?The pad in allegro is 0.1&0.3 ----two circles.

 

[greatmarx]

I check the geber files,found the finished hole diameter is 0.3mm not 0.1.
Thanks for your help.
regard
yang