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which verification methodology to be used??

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vlsichipdesigner

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system verilog behavioral synthesis

hi designers,

request you to throw some light on the verification methodology to be used for a chip

* what is the best verification language to be used?
* what all i need to take care to best design my testbench and to be portable , scalable across chips so that i can re-use the maximum.
* how to verify 3rd party IP's

Your thoughts/insights to verification methodology is required.

my prayers,
learn chip design freely no charges at all!!!
chip design made easy
https://www.vlsichipdesign.com
 

ljxpjpjljx

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Now System verilog is very good for verification , OVM and VMM , this two verification methodology you can refer!
Although if your design is related with some algothrim ,you can use System C to build your modeling!
 

dtn_me

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Recent trend has System Verilog as verification language to increase the portability and reuse of TB features. For communication between various layers of TB, OVM methodology is preferred.
 

amar2k904

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Hi ,

The verification methodology to choose depends on the design problem at hand.

1 ] complex Algorithmic design
design can be in systemc/verilog/vhdl
you can build testbench in systemc to verify the algorithmic model

Once you verify the algoritm , convert it into RTL using some behavioral
synthesis tools. the converted RTL again can be verified with the same
systemc testbench you used to verify the behaviural algorimic model.
similarly you can use the same testbench for GLS as well.
2 ] complex sdigital signal processing design
the same methodology mentioned above can be used.
People also use MATLAB in this case

3 ] Other designs
We have various HVLS and methodologies available today.

vera is comletely transforming into systemverilog
specman e is going to be there for some more time.

If the design is new , then it is always preferable to use
systemverilog based verification methodology OVM, VMM

both methodologies are powerful and having good support.
Since both methodologies are using the core systemverilog
language we dont have the problem of language.

When you compare openvera and specman e, both are completely
different languages and the methodologies built on them were incompatible.
systemverilog solves that problem . people can build their own methodology
using core systemverilog language


Systemverilog is the future of verification.

BR
Amar
 

anant

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Both VMM & OVM are good for designing testbenches using systemVerilog.
ovm supports all three popular languages systemVerilog, SystemC and e.
vmm supports only systemVerilog & runs with VCS only.
 

dtn_me

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Yes. You can say that the methodology we select depends upon tool or vendor.
If we use Synopsys VCS, we may have to choose VMM. If we go with Mentor, OVM is preferred.
 

powell_chow

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I do know little about the verification. But, I think the SystemVerilog is the best choice of verification.
 

paulki

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Hi,
Based on Tool cost, Uniqueness (in terms of both Design and Verification) System Verilog is the #1 choice, there are tools available in the market for Behavioral Synthesis (Cadence C-to Silicon). SO this can help you from the Architecture - Design -Verification closure easily.

Paul
 

ashiram

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Now a daya, Systemverilog has become very popular for functional verification.
Most of the companies changing their Verilog test bench to system verilog test bench.
Lot many OOPS concepts are introduced in systemverilog to achieve reuseability of data objects

Thanks,
RAM
 

jayTudu

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Use open source tools .... these are really very cool.......

Go for VIS tool. VIS is for LTL and CTL model checking .......
 

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