Which verification methodology is the best for RTL code?

[gayball]

Verification Methodology

hi,
If I want to verify the functional correctness of my RTL code, which method is the better choice to me. hdl-based? PLI-based? systemC-based or the others? Anyone can share your experiences? which do you think is the better?

 

[cawan]

Verification Methodology

is depending to the complexness of your design. For small to medium design, hdl-based testbench should be sufficient to verify your behavioral simulation. However, for high-level design which is more advanced in system based simulation, you should using sdl-based testbench such as system-C.

 

[gayball]

Verification Methodology

Thanks,
Is there any recommended document about SystemC?

 

[zhangpengyu]

Verification Methodology

You can find document in this forum!
Ohterwise , I think specman or vera is also a choice!

 

[zyphor]

Re: Verification Methodology

vera is a good choice

 

[tutx]

Verification Methodology

VERA is useful for your module level and also system level applications.

 

[soccer]

Verification Methodology

vera or specman is useful for your req.
vera for synopsys tools and specman for cadence tools

 

[AlexWan]

Verification Methodology

For my opinion, HDL and PLI is useful.
Vera or Specman need the relevant simulators. And they are supported by different vendors.

If you want to do verification, SystemC is a good language. If VSG accepts the SystemVerilog, I think it a good verification tool.

 

[alpha1]

Re: Verification Methodology

Thanks,
Is there any recommended document about SystemC?

SystemC from ground up is a good one

 

[niuniu]

Verification Methodology

I like system C, you do not need buy expensive tools. and it is very good to start from a high level design, where you have only pure C code.

 

[masai_mara]

Re: Verification Methodology

If you just want to verify the RTL which is implementing a moderate functionality then simply go for HDL test benches with maybe some PLI if required. If your design is complex with lot of hierarchiy then think of system C or proprietary ones like very and specman. But if you are new to system C it will take plenty of time to get it as you want. The proprietary ones need their simulators and licenses.

 

[quake]

Re: Verification Methodology

hi.
why not dry SystemVerilog. It is a little bit super and will be the trend, though there still are little tools supporting it.

 

[spauls]

Re: Verification Methodology

Hi,
U can use System C + Perl,
both are free of cost and accurate.

 

[haosg]

Re: Verification Methodology

I think that for communication chip, or protocol interpretion chip, the vera is very good, but for algorithm or data processing chip , the systemC is better

 

[appleleaf]

Verification Methodology

When you want to verify the RTL code, the better way is to use PLI. I think that it is the actual industry standard for extensive verification. Usually RTL test bench is limited in terms of stimulus generation.

 

[funzero]

Re: Verification Methodology

you can use the tools your corp have , but if you want to know how to verify your design , I recommended " writing testbench 1st Version" which can be download in the forum

 

[Arnold]

Verification Methodology

I think using systemc requires a long learning-curve, you can choose python, easy to use, easy to extend

 

[funzero]

Re: Verification Methodology

systemc maybe good choice , because of backupgound of c++,and easy to use for software programmer.