Which tools can do Layout Parasitics Extraction for ICs?

[tlihu]

I'd like to know more about the tools that can do LPE (Layout Parasitics Extraction) for ICs such as Hercules. :idea:

 

[cyteng]

lpe star rc

Cadence Dracula also can do it

 

[Nobody]

lpe　star rcxt

For 3D extraction , use mentor's Xcalibre instead .
And the linux version is available .

 

[moorhuhn]

raphael vs assura

There is also Assura RCX, successor of Vampire. Hierarchical, good
for large designs.

If you want to do parasitic extraction on the call based design,
you can use also Hyperextract (2.5D) - Cadence, or Fire&Ice Cadence
(former simplex).

 

[lassyy]

basic on lpe and extraction

Star-RC is good 3D LPE tool. And Star-rcxt is especially for Digital circuit LPE. But just for Sun-unix and HP-unix.

 

[cdic]

lpe hercules

no yet, the newest version 2002.2 is releasd and have linux distribution.

 

[chyau]

calibre lpe design flow

Hi,

I recommend Star-RC sofware.Because i know it can combind with raphael or raphael-nes(quicksim) to generator RC equeation to extract RC value.raphael and raphael-nes is standard RC-extractor in industry and all LPE tool will compare with them to calibration.So Star-RC accuracy is more than other LPE tools.

Best Regard,
chyau

 

[chyau]

lpe extraction

For 3D extraction , use mentor's Xcalibre instead .
And the linux version is available .

Hi,

If you want to extract a small block you can use xcalibre to do it.
If you want to exract a full chip or big block,i suggest you need use calibre-xrc to do it.
Because xcalibre speed is too slow.
above focus on Mentor extraction tool.

Best regards,
chyau

 

[bastos4321]

star rcxt lpe transistor

For a full chip usualy you do not want parasitic extraction, so it is possible to use just calibre LVS to get the netlist.

calibre -spice <outfile> LVSdeck_file


Bastos

 

[chyau]

For a full chip usualy you do not want parasitic extraction, so it is possible to use just calibre LVS to get the netlist.

calibre -spice <outfile> LVSdeck_file


Bastos

Hi,

If you want to do post-sim for top down design flow,you will need extract parasitic for a full chip(gate level) to generate a dspf file and use delay calculator(like as prime time) to generate a sdf file and do post-sim.
If you want to do post-sim for bottom up design flow,you will need extract parasitic for a full chip(transistor level) to generate lump C and so on..... and to do post-sim.
Could you tell me your design flow ? If you need to do post-sim,i think i want parasitic extraction.

Best Regards,
chyau