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I personally think that is better drawing your FSM in a piece of paper or electronically using Visio or something simple.
If you do the work properly :roll: and cover all the cases, and have a good testbench exercising all the inputs and states then you are all right and then you can use Synpl!fy FSM Extraction to compare the extracted FSM (nice graphical interface) with your piece of paper and see if you synthesized netlist matches with your specs.
Where I used to work, the two other FPGA designers (well, they called themselves like that, but that's another story... ) used Renoir for all their state machines and FPGA designs.
I have always refused to use these tools because I think that when you know what you are doing, the VHDL or Verilog code you will write is better than these tools and quite often you can do it in a shorter time. Also, by writing your own code, you are not tied to a specific tool vendor.
If you are not experienced using vhdl all these sort of graphical tools may help you to see the structure of the code and the relation with the graphical drawing, but once you have that knowledge I will forget the existance of that tool. Just think about manteinance, optimization, comments,...