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Which state machine editor are you using?

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skyglider

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I'm developing for Xilinx Spartan II and the question is, which state-diagram tool to use (from which package):

1. ISE
2. Active HDL
3. Visual Elite
4. Mentor
 

gnomix

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Personally in many years of work never I have used graphical tools to descrive a design.
I think that no graphical tool can be to reach the human engineer performance, but this is only a my opinion.
 

it_boy

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xilinx says we can acheive better result using the StateCAD which comes with ISE, but we too dont use any state-diagram tool in our company, we develop it manually
 

skyglider

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I agree, but such tool could be used to generate skeleton of the VHDL file and then add on features using hand coding. As I'm not experienced VHDL user ... I think this is a good way to start.
 

lollobrigido

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I agree!!!
When I've to develope discrete logic I use my hand...and perhaps in many case with vhdl. :roll:

regards
Lollo
 

maestor

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I personally think that is better drawing your FSM in a piece of paper or electronically using Visio or something simple.
If you do the work properly :roll: and cover all the cases, and have a good testbench exercising all the inputs and states then you are all right and then you can use Synpl!fy FSM Extraction to compare the extracted FSM (nice graphical interface) with your piece of paper and see if you synthesized netlist matches with your specs.

-Maestor
 

elvis

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Every project need to have high level design.
That's way, using such tools is matter of good practice.
I thing that MENT*R tools are nice.

Elvis
 

arena_yang

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I had ever used the StateCAD5.1 to implement a special sequence detection.I think that as someone mentioned previously we just can use the source codes generated to get a sketelon.

Of course,they are helpful but not useful!My own opinion!
 

snake

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i agree whit gnomix
i work whit vhdl and know that it´s much more powerfull than any other graphical interface

regards
 

mart242

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Where I used to work, the two other FPGA designers (well, they called themselves like that, but that's another story... :) ) used Renoir for all their state machines and FPGA designs.

I have always refused to use these tools because I think that when you know what you are doing, the VHDL or Verilog code you will write is better than these tools and quite often you can do it in a shorter time. Also, by writing your own code, you are not tied to a specific tool vendor.
 

zape

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If you are not experienced using vhdl all these sort of graphical tools may help you to see the structure of the code and the relation with the graphical drawing, but once you have that knowledge I will forget the existance of that tool. Just think about manteinance, optimization, comments,...
 

vvsvv

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StateCad!!!
 

Black Jack

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For FSM coding you MUST know basics
of state machines (Mealy, Moore, fsm coding-
binary, gray, one-hot fnd etc.)

and only manual coding :?
 

Git

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Notepad :)

Git
 

yerics

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I have use mentor FPGA-Advatage to design FSM,
It provides FSM animation function when simulation by modelsim

but I think it is of not so much help and prefer write FSM by manual coding.

Synplify also can extract FSM from design and optimize them (as they said)
 

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