Which simulator is better VCS or NC-verilog?

[DeepIC]

hi,all,

which simulator are you using? VCS or Nc-verilog?
i feel the VCS GUI is too simple and less powerful than
Nc-verilog. Do you think so?

deepic

 

[jiang]

vcs vs ncsim

I never use VCS, but I work with NC-verilog.
ncverilog 4.0 is more powerful than ncverilog 3.x, especially GUI and wave viewer.

 

[cnz]

vcs/ncsim

I love VCS,
but VCS simulates verilog only,LDV can simulates verilog and vhdl

 

[GoodMan]

verilog xl nc verilog differences

Hi all,

modelsim5.6 & NC-Sim ?

 

[asterix91]

vcs vs ncverilog

Model Sim has a good GUI but NC - Verilog is a lot lot faster when the simulation times are greater, especially NC-Sim for mixed mode simulation

 

[Laplace]

vcs simulations compile once

VCS is a compiled simulator. The compilation process takes longer but simulation takes shorter. I made a benchmark once between NC Verilog vs VCS, and I saw that VCS is 11 times faster than NC-Verilog.

 

[Ansunamu]

vcs vs ncverilog

althought i never used the VCS , i heart about vcs is used in big design

 

[DeepIC]

gui for ncverilog

VCS have DiretC and Vera-inferface,
is this reason to choice VCS?

 

[radix]

nc verilog vcs

Laplace,

I find it hard to believe that VCS is an order of magnitude faster than NC Verilog since NC is also compiled. The NC actually stands for "Native Compiled (or code or something)". Make sure that you're timing the simulations in both cases and not including the compile times since the compile should only happen when the netlist, not stimulus, changes.

The one feature, useful for verification, that VCS has is a switch that enables 2-state simulation. This feature can be useful for verifying startup conditions.

Radix

 

[Laplace]

vcs versus ncsim

Radix,

I checked my docs after your message, and saw that I am wrong. I made a benchmark between VCS and Verilog XL (the father of NC verilog) not NC-Verilog. I apologize for this mis-information.

 

[ttspice]

simulator vcs benchmark

i love nc-verilog, it has backward compability to verilog-xl,
many old designs are signed off with XL, once we find mismatch with
some old design, we can easyily convert the environment to XL,
and see if the problem is due to NC...


--try to collect more points

 

[silicon]

ncverilog 2state simulation

Does anyone know what is the last version of VCS?
Is the last VCS version with faster simulation speed than LDV 4.0?
And, how about the accuracy between them?

Silicon

 

[radix]

ncsim hsim vs vcs hsim

I think there is a version 7.0 that is going to be released soon. However, the latest version for d/l from their site is 6.2 which was released 7/15/02 for the DEC, HP_UX, IBM, Linux, and SUN platforms.

 

[radix]

vcs 与 ncsim

As a follow up I just found this press release, dated June 2002, on the Synopsys web page:

**broken link removed**

At the end of article they state the availability for version 7.0 as Q4 2002. Obviously, they're slipping a bit.

 

[ljkong]

convert ncverilog to vcs

all simulators have two mode. one is debug mode, one is performance mode.
so when simulation, you must know which your simulator is in.
good luck.

 

[aramis]

ncverilog, faster

VCS have DiretC and Vera-inferface,
is this reason to choice VCS?

Excuse me,
except VCS, is there any simulator tool support vera-interface??

 

[sigurdwang]

vcs pli debug mode

vcs is much faster than NC in the RTL level, but for gate level, vcs will be some problem

 

[shockie]

vcs versus ncverilog

I think VCS is very friendly to use for us with less powerfull function. and i would like to use nc-verilog. I have no the latest version of LDV. Would anyone like to tell me the different between the latest and 3.x version of LDV just about ncverilog.

 

[johnnyh]

difference betwenn vcs and ncverilog

more than 2M gate level simulation, NC-Verilog is better than VCS.

 

[kwkam]

performance vcs ncsim

The latest version of LDV is 4.10. I do know what is the difference between it and 3.x on performance. However. the GUI have improved and it replace signalscan with simvision.