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VCS is a compiled simulator. The compilation process takes longer but simulation takes shorter. I made a benchmark once between NC Verilog vs VCS, and I saw that VCS is 11 times faster than NC-Verilog.
I find it hard to believe that VCS is an order of magnitude faster than NC Verilog since NC is also compiled. The NC actually stands for "Native Compiled (or code or something)". Make sure that you're timing the simulations in both cases and not including the compile times since the compile should only happen when the netlist, not stimulus, changes.
The one feature, useful for verification, that VCS has is a switch that enables 2-state simulation. This feature can be useful for verifying startup conditions.
i love nc-verilog, it has backward compability to verilog-xl,
many old designs are signed off with XL, once we find mismatch with
some old design, we can easyily convert the environment to XL,
and see if the problem is due to NC...
I think there is a version 7.0 that is going to be released soon. However, the latest version for d/l from their site is 6.2 which was released 7/15/02 for the DEC, HP_UX, IBM, Linux, and SUN platforms.
I think VCS is very friendly to use for us with less powerfull function. and i would like to use nc-verilog. I have no the latest version of LDV. Would anyone like to tell me the different between the latest and 3.x version of LDV just about ncverilog.