Which signal to use as the input clock of DSM in PLL?

[share08]

i don't know which signal will be used as the input clock of the delta-sigma modulator in Fractiona PLL. the ref. clock or the clock divided by N-divider?
which is better, and why?
any suggestion is ok

 

[ieropsaltic]

Re: clock of DSM in PLL

You should use the output clock of the divider.
The reason is that you need the output of the DS to be synchronized with the divider. Meaning that you need the new division ratio to be loaded to the divider after the dvider finishes current division. If the refernce's clock is used, the division ratio may be changed before divider finishes division (note that refernce's edge and divider's output edge don't come at the same time).

 

[share08]

clock of DSM in PLL

thanks.