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This is very basic DFT qn. Familiarize yourself with controllability and observability principles. You need to disable the async pins otherwise during test/scan mode, they might get triggered and scan breaks....Your DFT tool will flag an error if it cant control async pin from top level or if it cant be repaired...Any basic DFT testbook should have sufficient material ...check couple of resources on **broken link removed**] its a blog run by very good dft expert.
1. making design controllable and observable...
2. So you initialize all design using the scan chain data shift in....(load)
3. also you will force primary input
Above all is making design having controlled, known state( value)
then you have make sure the response of the design is captured in the
scan chains flops...
to observe the response shift out the scan chain data out... (unload)
so if anything asyncronous you will not be having control on the even occurance
which changes the expected behavior of the logic(design) so it is difficult to expect a particular value...
So because of which tools give a DRC violations saying few inputs are not controllable ,