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Which one will dominate SystemVerilog or SystemC ?

What would yoy prefer: SystemC or SystemVerilog?

  • SystemC

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  • SystemVerilog

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thecat

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SystemVerilog

Hello,

All of us have heard about SystemC and that you can write synthesysable code in it as well as advanced tesbenches using the power of C. In the same time, now we learn about SystemVerilog which will contain Verilog2001 + a C extension to help system level design (not for synthesys I think) and verification, as well as writing software for the chip.

In my opinion SystemVerilog will be much better since all of ASIC designers are very used with Verilog and do not have to learn how to design synthesysable RTL code in C. What do you think?

For SystemC there is a tool from S-y-no-psssys CoCentric System Studio which I've heard it's the best (it also have a simulator for the SystemC code). For SystemVerilog I don't know of any tool yet. Do you?
 

joe2moon

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Re: SystemVerilog

thecat said:
Hello,
. For SystemVerilog I don't know of any tool yet. Do you?
From my point of view, SystemVerilog is better than SystemC in verification domain. Because Accellera has already accepted it as the SystemVerilog "standard" :!:

SystemVerilog (next-generation version of the Verilog) was introduced by Co-Design Automation, Inc. And this company has provided the simulator, named "SYSTEMSIM" to run the simulation. It also provides 'SYSTEMEX" to expand Superlog (now SystemVerilog) into the synthesizable subset syntax which can be accepted be the current logic synthesizer, such as $ynopsys' Des!gn Compiler.
(You can go to its website www.c0-design.com for more detail.)

Just a few weeks ago, the Co-Design Automation, Inc. has been acquired by $ynopsys. Good or bad ? Who knows ? But, one thing can be sure is $ynopsys has admitted the power of the Superlog and decide to support it !
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By the way, if you have experience about running the Verilog simulation with c-model, please reply the topic "VC$' Direct C or M0delsim's c-debug" on System-On-Chip forum to share it ! :eek:
 

thecat

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joe2moon,

Just to understand better: Systemlog was developed by Co-Design and then accepted by Accelera who renamed it into SystemVerilog?

I will aslo orefer SystemVerilog, but I see on the polll that there are more people that prefer SystemC.

In my opinion it's good that Syn o psys aquired Co-Design and I wonder if their tool CoCentric System Studio will also support SystemVerilog or they will make a new tool for that language.
 

joe2moon

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Sorry, I have made a mistake. :(

Co-Design Automation has donated its SUPERLOG Extended Synthesizable Subset (ESS) and Design Assertion language Subset (DAS) to Accellera.
And Accellera adopts them and adds them into Accellera's SystemVerilog standard.

So SUPERLOG is a superset of SystemVerilog.
 

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