Which language to write TestBench?

[davyzhu]

Hi all,

Which language you use or will use to write TestBench?

If you wish, please note why you choose/prefer this language? Thanks!

Best regards,
Davy

 

[nand_gates]

i will go for e its a powerfull HVL, SystemVerilog is also good but
still not fully supported by most of the EDA vendors and not yet stable!!
Need to find out which runs faster to produce same results. I hope
system Verilog will run faster!

 

[sp]

i only know verilog and vhdl...

i find out tht using verilog to do testbench is really easy (i am using it on VCS)...

however, i still think vhdl is better in doing hardware design (though verilog can do the same)... everytime i write vhdl, i will hav concurrent flow of the code in mind (not the case in verilog to me)...

regards
sp