Which language is beeterr for designing FPGA, VHDL or Verilog?

[hienpv]

i think verilog is esier to learn but it can't systhesis as high level as VHDL

 

[hienpv]

what do you think about Altera HDL language, AHDL?

 

[Daneshgar]

I started learing VHDL whit Xilinx VHDL MasterClass (Multimedia VHDL Tutorial for Xilinx Users) and first book that I use was VHDL primer .

e_learning www.drvhdl.com

 

[BlueSky68]

Re: VHDL or Verilog

Hi folks,

Why don't you guys start from SystemVerilog, I think it will the ultimate language for the ASIC/FPGA design very soon. It has incorporated the nice things of either Verilog or VHDL. Besides this, it also has a lot of verification features the none of these two languages has. As far as I know it also has assertion checking included.

Right now, Synopsys, Mentor are all support at least part of that. Cadence is going to support very soon.

As an ASIC/FPGA designer, honestly speaking, I finally see that one universal language that could do pretty much I want to do either in design or verification.

Regards,

 

[norton]

Re: VHDL or Verilog

Hi all,
I am researcher who is getting to know the basics of HDL now.I would like to know whether to learn VHDL or Verilog.My requirements are
that it should help me to rapidly design FPGA based controllers for my job.
Of course it should be easy to learn.In this regard which one should I try to study ? Thanks a lot.[/quote]

 

[homeadd]

If you want to learn,then you should begin.
If you do not,nothing is helping!
The key is that you begin to do,not want to do.

 

[Daneshgar]

Verilog is one of the two major Hardware Description Languages (HDL) used by hardware designers in industry and academia. VHDL is the other one. The industry is currently split on which is better. Many feel that Verilog is easier to learn and use than VHDL. As one hardware designer puts it, "I hope the competition uses VHDL." VHDL was made an IEEE Standard in 1987, and Verilog in 1995. Verilog is very C-like and liked by electrical and computer engineers as most learn the C language in college. VHDL is very Ada-like and most engineers have no experience with Ada.


Verilog was introduced in 1985 by Gateway Design System Corporation, now a part of Cadence Design Systems, Inc.'s Systems Division. Until May, 1990, with the formation of Open Verilog International (OVI), Verilog HDL was a proprietary language of Cadence. Cadence was motivated to open the language to the Public Domain with the expectation that the market for Verilog HDL-related software products would grow more rapidly with broader acceptance of the language. Cadence realized that Verilog HDL users wanted other software and service companies to embrace the language and develop Verilog-supported design tools.


Verilog HDL allows a hardware designer to describe designs at a high level of abstraction such as at the architectural or behavioral level as well as the lower implementation levels (i. e. , gate and switch levels) leading to Very Large Scale Integration (VLSI) Integrated Circuits (IC) layouts and chip fabrication. A primary use of HDLs is the simulation of designs before the designer must commit to fabrication. This handout does not cover all of Verilog HDL but focuses on the use of Verilog HDL at the architectural or behavioral levels. The handout emphasizes design at the Register Transfer Level (RTL).

 

[ZeleC]

i started with vhdl , but then when i heard that verilog is easier and that systemverilog is the future hdl , i tried to learn it but then i found it to be more difficult then VHDL !?
as a matter of fact i think the best hdl language is the one that u get used to ...

 

[Daneshgar]

VHDL is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Integrated Circuit. It can describe the behaviour and structure of electronic systems, but is particularly suited as a language to describe the structure and behaviour of digital electronic hardware designs, such as ASICs and FPGAs as well as conventional digital circuits.

VHDL is a notation, and is precisely and completely defined by the Language Reference Manual ( LRM ). This sets VHDL apart from other hardware description languages, which are to some extent defined in an ad hoc way by the behaviour of tools that use them. VHDL is an international standard, regulated by the IEEE. The definition of the language is non-proprietary.

VHDL is not an information model, a database schema, a simulator, a toolset or a methodology! However, a methodology and a toolset are essential for the effective use of VHDL.

Simulation and synthesis are the two main kinds of tools which operate on the VHDL language. The Language Reference Manual does not define a simulator, but unambiguously defines what each simulator must do with each part of the language.

VHDL does not constrain the user to one style of description. VHDL allows designs to be described using any methodology - top down, bottom up or middle out! VHDL can be used to describe hardware at the gate level or in a more abstract way. Successful high level design requires a language, a tool set and a suitable methodology. VHDL is the language, you choose the tools, and the methodology... well, I guess that's where Doulos come in to the equation!

Verilog is a Hardware Description Language; a textual format for describing electronic circuits and systems. Applied to electronic design, Verilog is intended to be used for verification through simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis.

The Verilog HDL is an IEEE standard - number 1364. The standard document is known as the Language Reference Manual, or LRM. This is the complete authoritative definition of the Verilog HDL.

IEEE Std 1364 also defines the Programming Language Interface, or PLI. This is a collection of software routines which permit a bidirectional interface between Verilog and other languages (usually C).

One important note: Don't confuse Verilog HDL with the Verilog-XL family of simulators. In the mid-80's, Gateway Design Automation developed a logic simulator, Verilog-XL, to simulate designs described using their proprietary Verilog HDL. Cadence have since bought Gateway and retained the Verilog-XL simulator, but the language, Verilog HDL, is now maintained by Open Verilog International (OVI). More on Verilog's history in the next Backgrounder article. In all of the pages on this Web site, when we refer to Verilog, we mean the HDL not the simulator.

Today, there is one and only one Verilog HDL. There are now many Verilog-related EDA tools available: formal verification tools, cycle-based simulators, logic synthesisers, timing analysers and ESDA design entry tools with Verilog support. There are of course slight differences between these tools in the aspects of the Verilog HDL that are supported. Not all simulators support the full Verilog HDL, for example.

Finally, VHDL is not an abbreviation for Verilog HDL - Verilog and VHDL are two different HDLs. They have more similarities than differences, however.

 

[renpzhou]

I think, both verilog and vhdl language should be
learned.For some books or progarmes are written
in one of the two languages

 

[semicon]

Verilog is one of the two major Hardware Description Languages (HDL) used by hardware designers in industry and academia. VHDL is the other one. The industry is currently split on which is better. Many feel that Verilog is easier to learn and use than VHDL. As one hardware designer puts it, "I hope the competition uses VHDL." VHDL was made an IEEE Standard in 1987, and Verilog in 1995. Verilog is very C-like and liked by electrical and computer engineers as most learn the C language in college. VHDL is very Ada-like and most engineers have no experience with Ada.


Verilog was introduced in 1985 by Gateway Design System Corporation, now a part of Cadence Design Systems, Inc.'s Systems Division. Until May, 1990, with the formation of Open Verilog International (OVI), Verilog HDL was a proprietary language of Cadence. Cadence was motivated to open the language to the Public Domain with the expectation that the market for Verilog HDL-related software products would grow more rapidly with broader acceptance of the language. Cadence realized that Verilog HDL users wanted other software and service companies to embrace the language and develop Verilog-supported design tools.


Verilog HDL allows a hardware designer to describe designs at a high level of abstraction such as at the architectural or behavioral level as well as the lower implementation levels (i. e. , gate and switch levels) leading to Very Large Scale Integration (VLSI) Integrated Circuits (IC) layouts and chip fabrication. A primary use of HDLs is the simulation of designs before the designer must commit to fabrication. This handout does not cover all of Verilog HDL but focuses on the use of Verilog HDL at the architectural or behavioral levels. The handout emphasizes design at the Register Transfer Level (RTL).

i agree.

 

[bagane]

verilog is easy to learn, so I choose it

 

[king002]

Verilog is simple...
And it is used more than VHDL in company..