true frequency
with out using SDF for gate leve simulation, you are trying to compare Apples with Oranges. Dont compare the results with STA and gate level simulation.
To check whether your constraints are complete or not, its a detailed process. somebody has to know about your design and special things inside your design, where we can apply multicycle paths, false paths. If your design doesnt have this kind of special schemes, put your interface and constarints. somebody can help you out what is missing in your constraints.