Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
NAND can be done by having transistors in series.
so the overall resistance will be greater compared to NOR with parallel transistors.
the delay is directly proportional to R.
the NAND will have more delay.
NOR gate only .This can be viewed from the circuit itself . You have a series connection of two PMOS of greater W/L (4 times that of nmos to have same rise and fall time ) . so this will increase the charging time in case ogf NOR gate compared to NAND gate .