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which company's 82c54 can be used under +3V ?

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wizz

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Thanks.
 

G

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Hi,

sorry but i don't know the exact answer to ur question but u should consider taking a low voltage cpld and put a free ip-core in it. This u can do for 3v and u will require less milliamps (if u choose right cpld)

Trotter
 

gabby

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Hi

The most comp that sold 82c54 are:

oki
intel
intersil
amd
umc
zilog
harris (not sure)


If you can't find the device (old chips) and also more rare for find 3.3v you can make yourself on clpd or fpga.

Best regards.
 

7rots51

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I think the best way is using fpga for your application ,I agree with gabby
 

wizz

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Hi:

Now my system use the CPLD "Crypress CY37064" which has 64 macrocells. Are the macrocells enough?

How many macrocells would be used in CPLD?
 

gabby

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Hmm...

Your chip have 64 macro that is ~1200 gate.
A full 8254 chip in vhdl have ~5000 gate, in fpga it use ~700 cell,
and in clpd i belive ~256+ (i think).

It's a bigest cpld.(a lot of cost in compare with the 8254 chip).

Try a 10k gates fpga from cypress if you like work with them,
i like more the fammily of 1k of @letra (you can use 1k10 all the system design) they are not exp(~15$ not sure) but you need work with that comp great & easy tool evaluation tool work with the most componnents.

Note: i don't know exactly what you need from the 8254, but i belive
that you don't need all the format work or all the timmers/counter,
you can desing yourself conuter/timmer that will more small then the
original core.

If you want declare what you need from the counter i can explain/design
you how to build and how much cell you will need.

Best regards.
 

gabby

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A simple (theorical) calculation for the 8254.


timmer 16 bit reg X3(you have 3) = 48 (flipflops=cells)
auto reload for timmer 16 bit X3 = 48
main control reg 8 bit = 8
control timmer reg 8 bit X3 = 24
interface 8 bit bus 8 bit = 8
timmer output 1 bit X3 = 3
functionnaly design ??? = ????
---------------------------------------------------------------------
total minimum know cells = 141+ cells

Best regards.
 

wizz

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Hi,gabby:

I only want two 16bit couter.

Now my 82C54 was used like that:
----------------------
3MHz --->| clk1
IO1------>| gate1
nc------->| out1

750k---->| clk2
IO2----->| gate2
nc------->|out2
------------------------
When IO is set high, the counter begins to count down (or count up) .
When IO is cleared, couter ends up and data is read by MSP430.

Well, How many macrocells would be used?

thx.
 

gabby

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Hi
You will need for simple desingn if i understand you correct(rpair me if you
need other changes).

(16bit counter +1 bit sync io to clock) X2 reg = 34 cells
+
8bit interface data bus = 8 cells
+
few cell for the control

i think 34+8+(2 or 4) = 44 to 46 cell in best case;



see a simple example in high level langue (translate it for your dev langue)
* the counter data will read correctly in this sample only when the counter is stop (i hope you drive the io for on of other is more complicate design).



declage

a[1..0] :input;
cs :input;
bus[7..0] :eek:utput tristate;

Funtion_clr_ctn_a : cell;
Funtion_clr_ctn_b : cell;

conuter_a[15..0] :dffe;
conuter_b[15..0] :dffe;
io_in_a :dffe;
io_in_b :dffe;

io_in_a.clk = clk_3mhz;
conuter_a[15..0].clk = clk_3mhz;

io_in_b = clk_750khz;
conuter_b[15..0].clk = clk_750khz;


io_in_a = io_a;
If io_in_a then
conuter_a[15..0] = conuter_a[15..0]+1;
else
conuter_a[15..0] = conuter_a[15..0];
endif;
conuter_a[15..0].clrn = Funtion_clr_ctn_a;


io_in_b = io_b;
If io_in_b then
conuter_b[15..0] = conuter_b[15..0]+1;
else
conuter_b[15..0] = conuter_b[15..0];
endif;
conuter_a[15..0].clrn = Funtion_clr_ctn_a;

if case a[1..0]

case a[1..0] == 0
bus[7..0] = conuter_a[15..8];

case a[1..0] == 1
bus[7..0] = conuter_a[7..0];

case a[1..0] == 2
bus[7..0] = conuter_b[15..8];

case a[1..0] == 3
bus[7..0] = conuter_b[7..0];

end case; -- (you can use also if elsif lines)

bus[7..0].oe = !cs & !rd; (cs can also be an adress decode fun in clpld like cs= a[12..6] == 347;) (carefull with static hazard on this funtion)

Funtion_clr_ctn_b = "finish read reg or write to the spec add reg func"
Funtion_clr_ctn_b = "finish read reg or write to the spec add reg func"

I hope that simple design answer for your question.

Best regards.
 

wizz

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Hi,gabby:

First, thank you very much!

You knew I use Cypress Cy37064.
But, when the program was compiled, I got errors like that:

"Output signal xxx can't assign logic block."

I think the macrocells must overflow.

I try to compile in CY37128(128macros). Succeed!

The result is:
These logics plus some other logics cost ONLY 58 macrocells.

Could you tell why?

If you puzzle too, do you mind to read my program?

thx.
 

gabby

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Hi wizz.

First i repair the line :i think 34+8+(2 or 4) = 44 to 46(not56) cell in best case;

Second.
Now after you tell me that the cost only 58 but the comp make eror in 64 macrocell, i belive that is because:

The clpd have a specific no wiring internal line that make the connection
btwen the lcells and the io , is small clpds (also more rare in big) when you
use over 80%-90% it have problem to fit that wires from the cells to cells or io.

The solve of the problem is don't fix the io but is no simple if you have design and evry compilation the io on the chpis are change.
The second option is to go to a bigger chip and that solve your problems in most case(are pins that you can't incrase evry time like special pins"clock" or cotrol for oe of outputs).


Thrid.

Is good reason from you if want to see how the end desing look.
"If you puzzle too, do you mind to read my program? "

It's simple ,first because your design in no big,
second design must no have puzzle.
The answer is on your hands, when you compile the sorce
you get some outputs file one of them for the cpld, but
you have a file that is report txt file.(some time you need to enable that
function on your compiller for get it).
In that file you can see evryting how was design,
how much cells and the equation for evry cell.


I'm an @ltera fammiliar design, but send to me the files (source and report) and i can tell you if i see some wrong i increase my know in other chips and comp. I pm my email.

A small note about the design i think we need to add also one more function
for know if the timmers got overflow(simple stop them when they gone to ffffh

declare
stop_cnt_a :lcell; --(force the comp to use cells for equation)
stop_cnt_b :lcell;

--"note"
-- ( you can use also node but in some case if the equation is over 16 signal he increase the cells on the cnt from 16 to Nx16 bacause that i use the lcell force, you can make a test with node and se that this cost you in cells if yes use the cell declaration that will cost only 1 cells)

stop_cnt_a = !(conuter_a[15..0] == ffffh);
stop_cnt_a = !(conuter_a[15..0] == ffffh);
(sorry for my spelling langue conuter =>counter)

repair lines :

1. If io_in_a then to => If (io_in_a & stop_cnt_a) then
2. If io_in_b then to => If (io_in_a & stop_cnt_b) then


Forth.
Note after you stop the counter from the io you must wait for one clock last of the counter before the data will valid for read.

Best regards.
 

wizz

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Hi, Gabby:

You must be a CPLD expert!

You said "The clpd have a specific no wiring internal line that make the connection." I think so.

I deleted one "Reset" signal and this problem was solved!
(The "Reset" signals was used in some functions!)

I have my program emailed to you.
(In the program, the error "Reset" code I have remarked with "Error Reset Signal" .)

Thanks again.
 

jzaghal

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Why not use a simple switcher ??

Hi,

Just a thought !! Did you consider using a simple 3 to 5V switcher to
only run the timer chip ??

Good Luck.
 

wizz

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Hi,jzaghal:

At first, I considered using 74lvc4245.

But, I must use three 74lvc4245s. The power consume was too high.

You know hand-hold meter can't cost too much current!

wizz
 

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