Which Cadence tools support fully SystemVerilog ?

[Bulma]

vcs/questa for systemverilog

Hi all, I have some questions really need your helps :

I've heard of Cadence tool named IUS. It seems to strongly support SystemVerilog. Anyone here tried this tool please share your experiences ...

1. Does it support all features & constructs of SystemVerilog ?
2. Can we reuse our old design IPs in new design using this new tool ? (Not counting on some syntax error may appears).
3. How fast is its speed ?
4. Which is IUS latest verion ?

Any reply is much appreciated ! Thanks in advance !

 

[claint]

systemverilog tools cadence

There is no tools of Cadence can fullu support systemVerilog.

 

[bigrice911]

actually, sv has not been fully supported by all the EDA vendors so far.
I think you can use IUS if you want to run sv codes in Cadence platform.

 

[aji_vlsi]

Hi Bulma,
I believe the best place for you would be support@cadence.com to get the most accurate and upto date answer. I had a meeting yesterday with them and they seem to be making good progress on SV. I will try and answer your queries as much as I can.

Hi all, I have some questions really need your helps :

I've heard of Cadence tool named IUS. It seems to strongly support SystemVerilog. Anyone here tried this tool please share your experiences ...

1. Does it support all features & constructs of SystemVerilog ?

Why do you need "all features" if not for an academic purpose? I would highly recommend to see "what you want to do with SV" and see whether the tool fits your needs. For instance IUS does support lot of Design and Assertions subset.

FYI - even V2K is not 100% supported by all major tools yet, so let's not bother about "all SV LRM constructs" - sure it will be nice to have that, but in my reading it will be 2010 before every major vendor can declare that result!

2. Can we reuse our old design IPs in new design using this new tool ? (Not counting on some syntax error may appears).

Yes it should and would - SV itself is defined to be well backward compatibility with Verilog.

3. How fast is its speed ?

Very relative question, NC has been quite fast and hence I believe it will maintain that lead. Sure the first few releases of IUS with SV may not optimize for speed, but they will work on that aspect soon.

4. Which is IUS latest verion ?

Any reply is much appreciated ! Thanks in advance !

Best to be answered by CDN folks!

Regards
Ajeetha, CVC
www.noveldv.com

 

[Bulma]

Thanks all for your replies !

Hi aji_vlsi, thanks for your detailed & helpful reply.

I've found some info about IUS, its lately version support almost all basic & strong features of SV which can improve our Verification performance.

However there're also many possitive comment about Synopsys' VCS. What do you think of it ? Moving to a new vendor is not a good idea ?

As for speed, even NCVerilog5.5 works more slowly than older verisons (have been tested). I'm really not so confident for its new versions in speed respect.

 

[aji_vlsi]

Bulma,

Thanks all for your replies !

Hi aji_vlsi, thanks for your detailed & helpful reply.

I've found some info about IUS, its lately version support almost all basic & strong features of SV which can improve our Verification performance.

However there're also many possitive comment about Synopsys' VCS. What do you think of it ?

VCS is certainly ahead (well ahead infact) in the race - as they drove this standard via their Vera language. Questa and NC are doing catchup in language - but the technology involved will take even longer to stabilize. So if you truly believe in competition, I would recommend an eval on your own (and BTW if you need professional assistance with such an eval, my company can help you with eval criteria, execution etc. - drop me an email via ajeetha <> gmail.com or www.noveldv.com).

Moving to a new vendor is not a good idea ?

Why not? That's the real idea behind standards! To increase competition - benefiting the end users.

As for speed, even NCVerilog5.5 works more slowly than older verisons (have been tested). I'm really not so confident for its new versions in speed respect.

Yet another reason for a good eval from your end. As I said before, tools are catching up in language support, stability in terms of performance, speed, memory, debug etc. is a long game with VCS in clear lead (BTW, I heard VCS lacks few constructs that Questa supports).

Also a good option to talk to Cadence and look to increase speed (else tell them you will look at VCS/Questa, then they listen)

Good Luck
Ajeetha, CVC
www.noveldv.com

 

[Bulma]

Also a good option to talk to Cadence and look to increase speed (else tell them you will look at VCS/Questa, then they listen)

Actually, it's not kidding idea at all. Waititng for Cadence IUS to mature for some more time is a good option.

Thanks aji_vlsi !

 

[vizpal]

Have u guys tried out Questa [Mentor] ??? This one supports most of the SV constructs than any other Synopsys or Cadence tool...
The latest version is Questa 6.2.... I'm working with it...
Questa 6.3 will roll out soon...