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Whether synthesis tool will realize comparators or not

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sky_above

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In a Verilog code for a design the if -else block is as follows inside a state named State5 of a FSM which is a block of the top design. Will the synthesis tool be automatically implement comparators to compare Input1 with Input2 and also another comparator to compare Input3 and reg6? In that case there is no need to write the RTLs for the two comparators. Here reg6 whose content is read by the FSM is a register inside the design. Input1, Input2, Input3 are inputs to the FSM.

Code: 
//Combinational part of the FSM
always @ (*)
begin: 

state0: ........
..............
..............
state5: if ((Input1 > Input2) && (Input3 <= reg6))

Enable=1'b0

else if  ((Input1 < Input2) && (Input3 <= reg6))

Enable = 1'b0;

else

Enable = 1'b0;

state6:
 

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