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Where to connect VCAP/VDDCORE pin on PIC24FJ64GA004?

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treez

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Hello,

I am using PIC24FJ64GA004 and i am not using the on-chip regulator. (i've disabled it)

-So do you know to what i should connect the VCAP/VDDCORE pin?

Page 21 of the datasheet says ..................


When the regulator is disabled, the VCAP/VDDCORE pin
must be tied to a voltage supply at the VDDCORE level.
Refer to Section 27.0 “Electrical Characteristics” for
information on VDD and VDDCORE.

However, section 27 doesnt tell how to connect this pin when the regulator is disabled.

PIC24FJ64GA004 DATASHEET:
http://ww1.microchip.com/downloads/en/DeviceDoc/39881D.pdf
 

bigdogguru

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I am using PIC24FJ64GA004 and i am not using the on-chip regulator. (i've disabled it)

-So do you know to what i should connect the VCAP/VDDCORE pin?

However, section 27 doesnt tell how to connect this pin when the regulator is disabled.
You answer lies in the quote from the device datasheet:

When the regulator is disabled, the VCAP/VDDCORE pin
must be tied to a voltage supply at the VDDCORE level.

Refer to Section 27.0 “Electrical Characteristics” for
information on VDD and VDDCORE.
If you disable the internal regulator, you must connect the VCAP/VDDCORE pin to a voltage supply at proper VDDCORE level.

The proper voltage range for VDDCORE is 2.0V to 2.75V, note a voltage below 2.35V will steadly decrease the maximum clock frequency of the device until 2.0V is reached at which point the devices maximum clock frequency is 16MHz.

A proper supply of VDD is still required, which can range from VDDCORE to 3.6V.





Reference: PIC24FJ64GA004 Family Datasheet, Section: 24.2 On-Chip Voltage Regulator, Page: 213

24.2 On-Chip Voltage Regulator

All of the PIC24FJ64GA004 family of devices power
their core digital logic at a nominal 2.5V. This may
create an issue for designs that are required to operate
at a higher typical voltage, such as 3.3V. To simplify
system design, all devices in the PIC24FJ64GA004
family incorporate an on-chip regulator that allows the
device to run its core logic from VDD.

The regulator is controlled by the DISVREG pin. Tying
VSS to the pin enables the regulator, which in turn, provides
power to the core from the other VDD pins. When
the regulator is enabled, a low-ESR capacitor (such as
ceramic) must be connected to the VDDCORE/VCAP pin
(Figure 24-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capacitor
is provided in Section 27.1 “DC Characteristics”.

If DISVREG is tied to VDD, the regulator is disabled. In
this case, separate power for the core logic at a nominal
2.5V must be supplied to the device on the
VDDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the VDDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 24-1 for possible
configurations.

24.2.1 VOLTAGE REGULATOR TRACKING MODE AND LOW-VOLTAGE DETECTION

When it is enabled, the on-chip regulator provides a
constant voltage of 2.5V nominal to the digital core
logic.

The regulator can provide this level from a VDD of about
2.5V, all the way up to the device’s VDDMAX. It does not
have the capability to boost VDD levels below 2.5V. In
order to prevent “brown out” conditions when the voltage
drops too low for the regulator, the regulator enters
Tracking mode. In Tracking mode, the regulator output
follows VDD, with a typical voltage drop of 100 mV.

When the device enters Tracking mode, it is no longer
possible to operate at full speed. To provide information
about when the device enters Tracking mode, the
on-chip regulator includes a simple, Low-Voltage
Detect circuit. When VDD drops below full-speed operating
voltage, the circuit sets the Low-Voltage Detect
Interrupt Flag, LVDIF (IFS4<8>). This can be used to
generate an interrupt and put the application into a
low-power operational mode, or trigger an orderly
shutdown.

Low-Voltage Detection is only available when the
regulator is enabled.


I'm curious as to why you feel disabling the internal regulator is necessary?

The device has an operational voltage range of 2.0V to 3.6V, without disabling the internal regulator.

BigDog
 
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treez

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i need to disable the internel regulator becasue its only 2 to 2.75V......and some of the voltages presenting at the PIC pins will be greater than that......up to 3.6V.......so i must power the PIC from 3.6V too.

Or have i got this wrong, is the 2 to 2.75V just an internal voltage that i can enable and forget about, and happily put voltages up to 3V6 on any pin?
 

keith1200rs

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Yes, you are wrong. The internal working voltage of the CPU is totally transparent to the user. Your I/O voltage will be whatever you use for VDD (and you can still use 5V I/O provided you set up the ports correctly on the 5V tolerant ones).

Keith.
 
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Tahmid

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The internal voltage regulator is used to drop VDD to 2.5V to power the core digital logic of the PIC24F at 2.5V. If you disable the internal voltage regulator, VDD must be about 2.5V. When you use 3.3V VDD, the internal voltage regulator must be enabled and you must connect the capacitor from VCAP to ground. The IO pins will be roughly equal to VDD when high, as the internal voltage regulator affects only the PIC24F core, but not the IO lines.



Hope this helps.
Tahmid.
 

bigdogguru

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If you disable the internal voltage regulator, VDD must be about 2.5V. When you use 3.3V VDD, the internal voltage regulator must be enabled and you must connect the capacitor from VCAP to ground.
Actually, your statement is incorrect.

If the internal voltage regulator is disable, the only requirement of VDD is the supplied voltage must be within the VDDCORE to 3.6V range, which includes the 3.3V level discussed.

VDDCORE can certainly by supplied by another voltage source as long as the supplied voltage remains within the 2.0V to 2.75V range.

Reference the middle configuration, internal voltage regulator disable, VDD supplied at 3.3V and VDDCORE supplied at 2.5V.




BigDog
 
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