you have 3 poles and one zero. The dominant pole is at the output - the only high impedance point in the circuit. The other pole is associated with the NMOS current mirrors and the third one with the PMOS current mirrors. The zero comes from the fact that the signal sees unequal paths to the input. One path is shorter - through one of the NMOS mirrors, directly to the output. The other path is longer, through the other NMOS current mirror and the PMOS current mirror to the output. This last one starts rolling off earlier than the first one, so there is a zero.