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well...we usuall use flip flop in digital design ,while cosidering the timing analysis it is better to use flip flop's... than latches...a latch is transparent during the entire level of the pulse...so it makes difficult for the designer to make sure that any hazard does not propagate to the next stage and affect the state in other latches...
But latches are used with flip flops for slack borrowing... if we use a latch in between two flip flops then since for a latch data can arrive even at the end of the clock pulse it facilitates the designer to have a component with longer delay infront of the latch yet can run the clock at slightly higher speed...
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