When to use Asynchronous FSM

[rogeret]

Hi,
I am doing a curriculum design and there is an FSM in it.
I an considering to use an asynchronous FSM, but I dont know the requirements to implement an asynchronous FSM and the merit of it.
And does DC or other EDA tool support it?
Thanks!
Rogeret

 

[yadavvlsi]

Different classes of asynchronous circuitry offer different advantages. Below is a list of the advantages offered by Quasi Delay Insensitive (QDI) circuits, generally agreed to be the most "pure" form of asynchronous logic that retains computational universality. Less pure forms of asynchronous circuitry offer better performance at the cost of compromising one or more of these advantages:

1. Robust handling of metastability of arbiters.
2. Early completion of a circuit when it is known that the inputs which have not yet arrived are irrelevant.
3. 70% lower power consumption compared to synchronous design
4. Possibly lower power consumption because no transistor ever transitions unless it is performing useful computation (clock gating in synchronous designs is an imperfect approximation of this ideal). Also, clock drivers can be removed which can significantly reduce power consumption. However, when using certain encodings, asynchronous circuits may require more area, which can result in increased power consumption if the underlying process has poor leakage properties (for example, deep submicrometer processes used prior to the introduction of High-k dielectrics).
5. Freedom from the ever-worsening difficulties of distributing a high-fan-out, timing-sensitive clock signal.
6. Better modularity and composability.
7. Far fewer assumptions about the manufacturing process are required (most assumptions are timing assumptions).
8. Circuit speed adapts to changing temperature and voltage conditions rather than being locked at the speed mandated by worst-case assumptions.
9. Immunity to transistor-to-transistor variability in the manufacturing process, which is one of the most serious problems facing the semiconductor industry as dies shrink.
10. Less severe electromagnetic interference (EMI). Synchronous circuits create a great deal of EMI in the frequency band at (or very near) their clock frequency and its harmonics; asynchronous circuits generate EMI patterns which are much more evenly spread across the spectrum.
11. In asynchronous circuits, local signaling eliminates the need for global synchronization which exploits some potential advantages in comparison with synchronous ones. They have shown potential specifications in low power consumption, design reuse, improved noise immunity and electromagnetic compatibility. Asynchronous circuits are more tolerant to process variations and external voltage fluctuations‎.
12. Less stress on the power distribution network. Synchronous circuits tend to draw a large amount of current right at the clock edge and shortly thereafter. The number of nodes switching (and thence, amount of current drawn) drops off rapidly after the clock edge, reaching zero just before the next clock edge. In an asynchronous circuit, the switching times of the nodes are not correlated in this manner, so the current draw tends to be more uniform and less bursty.
Asynchronous circuit - Wikipedia, the free encyclopedia
**broken link removed**

 

[rogeret]

Thanks.
But does the asynchronous circuit especially asynchronous FSM supported by automated synthesis tool NOW?

 

[FvM]

What's the your hardware target? Asynchronous design is effectively unsupported by FPGA tools, for various reasons, it may have fields of applications with ASIC. yadavvlsi's comment sounds somewhat theoretically to me. Isn't it that nearly all ASIC designs are still done synchronously? Is this only due to designers ignorance?

 

[rogeret]

thanks. both fpga and asic may be my target, for i just wanna get a general understanding.
BTW, the Unsupport may also due to the difficulty in STA.

 

[FvM]

BTW, the Unsupport may also due to the difficulty in STA.

That's surely part of the problem. An important point is the behaviour of FPGA LUT-based logic elements, that don't guarantee glitch-free operation with multiple inputs changing simultaneously.