Feb 6, 2008 #1 S sally wang Newbie level 5 Joined Jan 2, 2008 Messages 10 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,336 ques on Verilog HDL in Verilog HDL, when should I use 'assign', and when use 'always'? Anyone understands this area can help me modify this Verilog code? module led1(CLK,SMP,OVR,UPL,TRG); input CLK; output SMP,OVR,UPL,TRG; always @ (CLK) SMP <= 1'b0; OVR <= 1'b0; UPL <= 1'b0; TRG <= 1'b0; endmodule
ques on Verilog HDL in Verilog HDL, when should I use 'assign', and when use 'always'? Anyone understands this area can help me modify this Verilog code? module led1(CLK,SMP,OVR,UPL,TRG); input CLK; output SMP,OVR,UPL,TRG; always @ (CLK) SMP <= 1'b0; OVR <= 1'b0; UPL <= 1'b0; TRG <= 1'b0; endmodule
Feb 6, 2008 #2 omara007 Advanced Member level 4 Joined Jan 6, 2003 Messages 1,237 Helped 50 Reputation 102 Reaction score 16 Trophy points 1,318 Location Cairo/Egypt Activity points 9,716 ques on Verilog HDL Try this link : https://www.asic-world.com/verilog/synthesis3.html
Feb 6, 2008 #3 master_picengineer Banned Joined Sep 3, 2007 Messages 848 Helped 66 Reputation 132 Reaction score 16 Trophy points 1,298 Activity points 0 ques on Verilog HDL Hi, Find your response inside this document: #975430