when to fix transition and capacitance violation during PnR?

[chris_li]

Hi Guys, transition(slew) and capacitance are "Design Rule Constraints" (Synopsys called it "DRC") specified in library. But I am not sure when to fix the violation during P&R is the most efficiency without affect existing timing or next step operation?

1, After Placement ?

2, After CTS ?

3, After final routing ?


Thanks.

 

[kbulusu]

More early you do, the better you are during timing closure and from routability point of view..if you do very late after final routing, tool might insert tons of buffers to fix the slew viol and you might have local hotspots and drc closure might become night mare...since CTS is also done, it affects hold and so timing closure is also difficult...so wait till the final stage is done and do everything..thats very bad practice and not advisable...so bottom line is fix the viol as much as you can and as early as possible...when you go to next stage, new viol might popup again, but it will be small and better manageable than if you leave everything on the table..

hope this helps...good luck with your timing closure...