When input affects Biasing

[kaps_nit]

While doing some experiments in Lab I found that most of the time the signal voltage affects the biasing voltage. say for exaple, yesterday i was doing Schmitt trigger (with reference) experiment, i found that for a very low value of input the transfer characteristic gives desired result but as input value increases the hysteresis voltage starts changing which is not desired. Can u suggest me how to control that unwanted effect??

 

[p.mlo]

The histereze characteristic isn't ideal, when the input voltage rises on a very high level the voltage at output slightly increses also. I recall that's caused by the triggers structure (capacitance inside the µchip). I would search for any Schmitt trigger producer's datasheet, maby there is a parameter for that.