Hi dftrtl
clock gating to be high or low depends on the way flip-flop edge is referred.
If u write a flop with negedge of clock then u go for gated clock to high. When it is posedge of clock then clock gated will be low, in order to turn off the flip-flop. So, that there is no transition b/w states in flip-flop.
What actually clock gating does is it turns off the transition in flip-flop.
let me give an example:
always@(posedge clk)
if (reset)
d<= 'b0;
else
d<= in ;
in the above case there wont be any clock gating becoz when ever there is poedge on clock there is transition.
always@(posedge clk)
if (reset)
d<= 'b0;
else if(en)
d<= in ;
if we take the above case when there is en or reset, then only the flip-flop is enabled with clock or else the clock is turned off to the flip-flop. It is like u won't get the 50% duty cycle on clock.
This turning off the clock(clock gating) is done by tools like Design compiler if clock gating constraints are set.
If gated clock is high for a posedge triggered clock then the flip-flop goes on triggered.
Flip-flops can retain their values without clocks by just giving power supply. So, if we turn off the clock the power is saved.