When and why should we use pipelining in FPGA?

[TrickyDicky]

what do you mean by "structural modelling"?
Usually, you draw out your circuit on paper before writing VHDL, then you write the code to describe your circuit. can you post some of your code?

 

[vineetkumar1992]

i have coded the component according to project (floating point multiplier) and then am using them by declaring and instantiating them in main program.
the code is attached.
comp_exponent_cal is the main file and i want to pipeline between unsigned_exponent_adder and rilpple_borrow.
please tell me how??

 

[TrickyDicky]

wow, this really is a back to basics design.
You have written this at a very basic low level. To pipeline it at this level, you will probably have to re-write it with registered added it wherever required (which will be after every adder, and other blocks). You will also have to bring the clock as a port into every entity.

For floating point, I highly suggest using the floating point IP cores provided by the vendors (for free).

 

[vineetkumar1992]

yes it is very basic level design and thanks..
can i use parallel in parallel out resister(using d flip flop) between two stages for pipelining
or
only use clock with if statement under process declaration inside the components.

 

[TrickyDicky]

do you mean register?

you could try having them between stages, but it doesnt lead to a very well planned design.
Personally, I would have put all the registers in with the origional code.

 

[vineetkumar1992]

and the 2nd option that i think for pipelining

to use clock with if statement (IF clk'EVENT AND clk = '1' THEN) under process declaration inside the components

is this technique is suitable/applied for pipelining??

 

[TrickyDicky]

not only is it suitable, it is how most people do it.