when a counter count?

[sheikh]

Hello Dears
Could you please tell me when a counter in a control unit ( a datapath controller) must count? I mean, it count when a new input arrived or count when an out released. Also, how can I insert a counter in a vhdl code of a control unit. Is it necessary to use component of a counter in vhdl code of a control unit or not?

Regards
Mostafa

 

[TrickyDicky]

a counter counts whenever it is enabled.

This is a very vague question. can you be more specific.

 

[K-J]

Hello Dears
Could you please tell me when a counter in a control unit ( a datapath controller) must count?

It must count when commanded to count...asking it to count is generally not enough

I mean, it count when a new input arrived or count when an out released.

It depends, there are several possiblities...
- Count on new input if properly designed to count new incoming events
- Count on out released if properly designed to count when out things are released.
- Basically never count if the counter is properly designed and is supposed to be counting proton decay
- Count occasionally if not properly designed

Also, how can I insert a counter in a vhdl code of a control unit.

Start by creating a counter...once that is working maybe you'll have additional questions or maybe after having gone through that effort it might be clear to you at that point, I don't want to assume one way or the other.

Is it necessary to use component of a counter in vhdl code of a control unit or not?

Not

Kevin Jennings

 

[sheikh]

Thanks a lot Dear Kevin.

@ dear mrflibble i am not Shakespeare ;D

more specific dear TrickyDicky

well I designed this sequence of loads (fig) and want to stop it at "T5" after reading the elements of a file. consider " end_file" as a condition that stop the process, now as i said I don't know how to use a counter in vhdl code of a"control unit" to count the file elements and after file finished set "end_file" to 1.( as like as program counter)

in code XYZ ar inputs and F1 and F2 are outputs

 ------------------------ combinational part of state machine---------------------

  combinational : process(present_state, END_File)
  begin
    case present_state is
      when RESET =>
        next_state  <= T0;
      when T0 =>
          next_state <= T1;
      when T1 =>
          next_state <= T2;
      when T2 =>
        next_state <= T3  ;   
	  when T3 =>
        next_state <= T4;		
	  when T4 =>
        next_state <= T5;
	  when T5 =>
	    if (END_File = '1' ) THEN
		    next_state <= FINISH;
		else
		   next_state  <= T4;
		end if;
     when others =>
        next_state <= FINISH;
    end case;
  end process combinational;
  T0_state    <= '1' when (present_state = T0) else '0'; 
  T1_state    <= '1' when (present_state = T1) else '0'; 
  T2_state    <= '1' when (present_state = T2) else '0'; 
  T3_state    <= '1' when (present_state = T3) else '0'; 
  T4_state    <= '1' when (present_state = T4) else '0'; 
  T5_state    <= '1' when (present_state = T5) else '0';  

 
              --- Load Sequences ---

  L_X       <= T0_State or T2_State or T4_State;
  L_Y       <= T0_State or T2_State or T4_State;
  L_Z       <= T0_State or T2_State or T4_State;
 
  L_C1       <= T1_State or T2_State or T3_State or T4_State or T5_State;  
  L_C2       <= T1_State or T2_State or T3_State or T4_State or T5_State;
  L_C3       <= T1_State or T2_State or T3_State or T4_State or T5_State;

  L_C4       <= T2_State or T3_State or T4_State or T5_State;
  L_C1_1     <= T2_State or T3_State or T4_State or T5_State;
  L_C3_1     <= T2_State or T3_State or T4_State or T5_State;

  L_C5       <= T3_State or T4_State or T5_State;
  
  L_F1       <= T4_State;
  L_F2       <= T5_State;

**broken link removed**

Regards
Mostafa

 

[TrickyDicky]

Its still not very clear.

whats wrong with something like this:

process(clk)
begin
  if rising_edge(clk) then
    if present_state /= T5 then
      count <= count + 1;
    end if;
  end if;
end process;

 

[sheikh]

well it just count the number of state. if you see the figure i want to go from T5 to T4 and when read all file values ( for instance 100 values) then go to finish state.
can I change it like this?

process(clk)
begin
  if rising_edge(clk) then
    if (count /= 100 and present_state = T5) then
      count <= count + 1;
      next_state <= T4
     else
       next_state <= Finish;
    end if;
  end if;
end process;

Thanks

 

[TrickyDicky]

yes you can. Why not try out your code in testbenches rather than ask here?