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what's wrong with this GainBoosted OPA

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wjxcom

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Hi all: I am designing a GainBoosted OPA, now there have some questions that needed to be resolved!

The load of the OPA is 1.5pF, and the GBW of the OPA is 300MHz.

At first, I design the MAIN OPA of the GainBoosted OPA and the GBW of the MAIN OPA is 300MHz, the load of the OPA is 1.5pF, the phase margin of the MAIN OPA is 53.

After designing the MAIN OPA, I design Nmos_INPUT AUXILIARY OPA and Pmos_INPUT AUXILIARY OPA. The GBW of the Nmos_INPUT AUXILIARY OPA is 373MHz, the load of the OPA is 0.6pF, the phase margin of the MAIN OPA is 84; The GBW of the Pmos_INPUT AUXILIARY OPA is 381MHz, the load of the OPA is 0.6pF, the phase margin of the MAIN OPA is 84.

But after the simulation, I found that the The GBW of the GainBoosted OPA is 336MHz, the phase margin of the GainBoosted OPA is only 20(the load of the OPA is 1.5pF).

I think the pole and the zero shoul be at the unity-gain frequency, so if the phase margin of the MAIN OPA is 53, the phase margin of the GainBoosted OPA should be 53, I do not know why the phase margin of the GainBoosted OPA is only 20?

Help me, please. thanx!!

The full schematic and the netlist of the OPA can be found at the attachment: the gain_boosted.pdf is the MAIN OPA; the auxiliary_n.pdf is the Nmos_INPUT AUXILIARY OPA; the auxiliary_p.pdf is the Pmos_INPUT AUXILIARY OPA; cmfb_n.pdf is the CMFB circuit of the Nmos_INPUT AUXILIARY OPA; cmfb_p.pdf is the CMFB circuit of the Pmos_INPUT AUXILIARY OPA; the opa_bias_improve.pdf is the BIAS circuit of the GainBoosted OPA and the AUXILIARY OPA; balun.pdf can be used to AC simulation; the Gain_Boosted_ac.sp is the netlist of the OPA, and the csmc.lib is the library file of the OPA.
 

hr_rezaee

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Hi
I think your aux. amp are in triode (I didn't simulae it, it is a guess.)
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    wjxcom

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wjxcom

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Hi hr_rezaee: I have already simulate the aux.map, and I do not find the aux. amp are in triode.

why do you think the aux. amp are in triode?

regards
 

hr_rezaee

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Hi
because
VGS6 of main is equal to VDG2 of N-aux amp.
so, VDG2=VGS6 and maybe bigger than VT.
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    wjxcom

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wjxcom

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Hi hr_rezaee: why VDG2=VGS6 and maybe bigger than VT??
I simulate the circuit, thay are in saturation region!

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wjxcom

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Hi hr_rezaee, it is kind of you to reply my topic, thanx! the N-aux amp is in saturate.

I use Hspice and use .PZ to simulate the OPA, after the simulation, though a zero and a pole point were found at the 335MHz at the wave, I do not find the pole and the zero at 335MHz in the file .lis. I do not know why!!!

Help me please, thanx!!!
 

hr_rezaee

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Hi
I simulate your circuit
I think you must reduce Wu of aux amps.
I'm not sure see Bult's paper .
regards
 

    wjxcom

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wjxcom

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Hi hr_rezaee: thanx you again to reply my topic!! At the same, what is the title of Bult's paper?
 

wjxcom

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Hi hr_rezaee:I have read this paper. As descibed in this paper, if the unit frequency and the second pole of the main opa is w4 and w6, I make the unit frequency of the auxiliary OPA "wu" :w4<"wu"<w6. so in my design, the wu is 335MHz, and at the region: w4<"wu"<w6.

So hr_rezaee, would you help me again? thanx you!!!!
 

hr_rezaee

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Hi
I reduced size of M00 in two aux amp. (it means that I reduced current of aux amps and so, gm of input transistor and so, Wu of aux amps).
and I saw that PM (pase margin) was too better than ago.
try this (you must redesign aux amps for better answer)
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    wjxcom

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wjxcom

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Hi hr_rezaee, I reduce the size M00 in two aux amps and I found that the PM is better than before!

But I have question: if I reduce the size, i.e. reduce the Wu of aux amps, then the equation (4) which was mentioned in the paper "A fast-settling CMOS op amp for SC circuits with 90-dB DC gain" writed by Bult wil not be satisfied, is it? so why the PM is better now??

Hi hr_rezaee, it's kind of you to help me, thanx!!!
 

jeffsky520

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Hi, did u try to reduce sizes of M5~M8 in main AMP for better PM?
 

    wjxcom

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hr_rezaee

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Hi
I'm not sure
but I think you measure the band width of aux amps wrongly.
I think you must measure capacitance at the gate of M5, M6, M7 and M8.
then use this capacitor as load of aux amps.
maybe it helps you.
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    wjxcom

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wjxcom

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Hi jeffsky520: when I reduce the I use the sizes of M5~M8 in main AMP, then the gain of main AMP will be reduce!!

Hi hr_rezaee: I use this sentence to meare the capacitance at the gate of M5, M6, M7 and M8, i.e.
".OPTIONS POST BRIEF NOMOD CAPTAB ACOUT=0 CSDF=2 PROBE",
I'm not sure if my measure is right! would you give me some advice to measure the capacitance at the gate of M5, M6, M7 and M8??

thanx!!!
 

wjxcom

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Hi hr_rezaee: I'm sorry to disturb you again! but what's your meas of "CAPTAB is good"?

thanx!!!
 

hr_rezaee

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Hi
see simulation results:

captab:
0:eek:utnn = 1.4726p
0:eek:utnp = 1.4726p
0:eek:utpn = 2.0139p
0:eek:utpp = 2.0139p


auxn:
gm1=3.9659m Cl=1.4726p Wu=428.62 MHz

auxp:
gm1=4.8700m Cl=2.0139p Wu=384.86 MHz

main:
gm1=5.0128m Cl=1.5p Wu= 531.87 MHz

in bult's paper:
w3<w4<w6
see fig. 3

so,
it is a bad design.
you must reduce Wu of aux amp
redesign it.
regards
 

    wjxcom

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