what's wrong in my verilog code ?

[vaf20]

hi
this is my Basic Question
suppose we have 3 signal's named A,B as input's and C as output.
C should be high by positive edge of B and should be low by negative edge of A.the simplest code is following :
//
always @(posedge B) C <= 1'b1;
always @(negedge A) C <= 1'b0;
//
or other way
//
always @(B)
begin
if(B) C <= 1;
end
always @(A)
begin
if(!A) C <= 0;
end

what's my wrong since it does not implemented in a CPLD and have a synthesis error :

ERROR:Xst:528 - Multi-source in Unit <.> on signal <C>
Sources are:
Signal <C> in Unit <.> is assigned to VCC

tnx

 

[semiconductorman]

your first case i.e,
always @(posedge B) C <= 1'b1;
always @(negedge A) C <= 1'b0;

Most synthesis tool when they see posedge try to synthesise a flipflop with the clock equal to the paramenter in sentivity list . But you have 2 conditions , one in which B is to be used as clock and other in which A is to used as clock . This is not possible. Even for simulation only purpose this is not the best code .. because of race condition . what happens if posedge of B and negedge of A happen at the same time ??????
------
Your second piece of code
always @(B)
begin
if(B) C <= 1;
end
always @(A)
begin
if(!A) C <= 0;
end

First always infers a mux if which B is select line of a 2 input mux , The input[1] is connect to VCC. and input[0] of mux is left open .. and output is connected to 'C' ,same type of circuit is infered by second always block except here input [0] is connected to GND and input [1] is open and output is connected to 'C' ... this is clearly a case where you are trying to drive a point 'C' from multiple locations hence the error! Again even for simulation only purpose this causes a race condition ... please try to synchronise with A and B with some clock if you intended to make a proper code ... If this is a piece of code which is a part of a larger code ... put up your issue .. probalby we can come to some other solution

Added after 1 hours 32 minutes:

Sorry I got the second analysis wrong this does not produce muxes as I had suggested but will create Latches with input connected to VCC for first always and Latch connected to GND for second always , and the clk in first case is B and second case is A and both of them will try to drive point C ... Multiple driver at 'C' . This is the problem !

 

[z81203]

always @(A or B)
begin
if(B) C <= 1;
else
if(!A) C <= 0;
end

just like dff with set & reset.

 

[Thomson]

Some coding styles should be adhered to if correct synthesized results are expected.
(1) don't assign the same signal in more than parallel procedures. otherwise the error information that multi sources with one signal will be generated.
(2) always with edge-triggered block will infer registers.
(3) if combinational logic is required, don't use non-blocking assignments(recommended)

 

[jay_ec_engg]

Simple answer....

What if rising edge of B and falling edge of A occur at the same time....?? How ur code should work ??????

 

[supercst]

can't have two edge trigger device.

 

[maxer]

avoid always double trigger on the same process..

i would suggest to split the PGT and the NGT in two different processes... and then use the results...

regards

maXer

 

[phoenixfeng]

coding style

 

[nand_gates]

Hi vaf20,
I think this is what you are looking for!!

module phase_detector (A, B, C);
   input A, B;
   output      C;

   reg         C;
   reg         D;
   
   wire        reset_n = ~(C & D);
   
//FF 1 with A as clk 
   always@(posedge A or negedge reset_n)
     if (!reset_n)
       C <= 1'b0;
     else
       C <= 1'b1;
//FF 2 with B as clk
   always@(posedge B or negedge reset_n)
     if (!reset_n)
       D <= 1'b0;
     else
       D <= 1'b1;
endmodule // phase_detector

Verilog is a HDL means you first think about hardware you want and then use
verilog to just describe it!
- my Verilog Guru

 

[revanth]

dude,

juat as jay_ec_engg told, there should be some resolution logic, when both the events are happening at the same time.
because two alwasys blocks are desiging the same flip- plop, both will try to push contrary logic-states, and output will be indeterminate state.

better not to use posedge and negedge, at a time in teh design.

"enjoy your work"