vhdl initial values
Hi,
There are 2-3 ways to achieve the similar results:
1.
Process statement without sensitivity list and a wait (only wait; not wait on/for etc.) statement as last statement in process.
Process statement will execute once and will be suspended on wait statement. Hence wait statement should be the last statement of process.
2. Give initial values to signals while declaration. In example below signal flag_sig will be initialized to '0'.
SIGNAL flag_sig : STD_LOGIC := '0';
Problem with this method is that initial values are generally not supported by synthesis tools, so the design behavior in actual hardware may not match with simulation results.
3. This is the best way to achieve the goal. You can say almost all the devices require Power-On Reset. As reset should be there in your design, you can specify reset values for all signals in your design. On power up, reset should be applied to chip as a result initial values are assigned to the corresponding signals.
Regards,
JItendra