What's the use of "&" operator in VHDL?

[nge]

Hi all,

I need help with the VHDL operator '&'. In some documents, it's been listed as bitwise AND operator but in others it's a CONCATENATION operator. In active-help online help, the first page said it's CONCATENATION and on the next page it's bitwise AND. I really need help. Thanks.

Nge

 

[air]

vhdl bitwise or

& is concatenation sign without any doubt

 

[chaitu2k]

bitwise or in vhdl

& - concatination

and - bitwise and operation

any VHDL book will tell u this

 

[ikru26]

concatenation operator vhdl

The & operator is a built-in VHDL operator that performs the concatenation of bit_vectors. For example, with the following declarations:

signal a: bit_vector (1 to 4);

signal b: bit_vector (1 to 8);


The following statement would connect a to the right half of b and make the left half of b constant '0'.

b<="0000" & a;

The & appends the a to the end of the "0000" to form a result that contains 8 bits.

Operator: &

The concatenation operator. Each operand must be either an element type or a 1-dimensional array type. The result is a 1-dimensional array type.

hope u r clear now

 

[adap]

vhdl concatenation operator

It's a concatenation operator in VHDL.
In Verilog works as a bitwise AND operator.

 

[amir81]

vhdl and bitwise

"&" is only for concatenation. see ieee standard of vhdl for more information