What's the use of free-running clocks?

[pandit_vlsi]

hi all.
i am working placement step in asic flow.
i come across a word free-running clocks.
what is the use of these clocks....
why those r removerd while CTS.


thanks in advance.
Pandit.

 

[research235]

FREE-CLOCK

hello Pandit
I am not sure if this answer is correct ,, please let me know if I wrong ..

In the asic flow wen u start with DC for synthesis, the design is synthesised for timing requirements b4 even the actaual clock is placed.. which is done only CTS level .. so in order to check for the timing requierements during synthesis level .. its takes internal lib files .. may be at this stage the FREE running clock are placed which are taken off during the actual CTS ..

please correct me ... coz i am just assuming this and i am also very new to ASIC. design

suresh

 

[spauls]

Re: FREE-CLOCK

I beleive this for Synthesis with higher periods.