What's the relation between Hold Time and Clock-to-Q Time ?

[omara007]

Hi folks

For a given storage device (FF, Latch, Memory Array, etc.), what is the relation between Hold-Time and Clock-to-Q Time ?

Regards

 

[aravind]

u can read from library file itself.
otherwise if u wanna see easy
report library command.

 

[omara007]

Re: What's the relation between Hold Time and Clock-to-Q Tim

u can read from library file itself.
otherwise if u wanna see easy
report library command.

can u explain more ?

 

[roohi]

Re: What's the relation between Hold Time and Clock-to-Q Tim



hi

CQ + combination > Thold +skew

this condition has to be satisfy for proper opertaion of a circuit oter wise it goes into metastability.

regards

roohi

 

[zhustudio]

Commonly, The CLK-Q timing is no less than its hold time in the library cell.
So if you design a ideal clock network (skew=0), and FF after FF, there will be no hold time violation.

But CLK-Q and hold time does not have closely relation, because one is descripting the input pin and the other is for output

 

[jjww110]

no relation,hold time is determined techonology lib,

 

[omara007]

Re: What's the relation between Hold Time and Clock-to-Q Tim

hi

CQ + combination > Thold +skew

this condition has to be satisfy for proper opertaion of a circuit oter wise it goes into metastability.

regards

roohi

I guess Roohi is correct ..

 

[AlexWan]

I agree aravind and jjww110. There is no relation between CQ and hold time of a memory element. Those two data are solid after cell definition.

If the design can't be suitable to roohi's formulary, designer has to choose another cell. But the CQ and hold time of new cell is solid.

 

[calm]

what is the Clock-to-Q Time?

 

[incisive]

Re: What's the relation between Hold Time and Clock-to-Q Tim

The formula given by Roohi is the right one. The timing is met if the above condition is met.

Regards