What's the purpose for avalanche capability test of power MOSFETs/IGBTs?

[hndxwzq]

Hi, All, I am very confused on the failure test of power devices.

As well know, the short-circuit capability test of power mosfets/igbts can be used to determine and design the fault response time of a overcurrent protection circuit.

1. So how about the avalanche capability test of power mosfets/igbts? To determine and design a fault response time for a overvoltage protection?
Actually, many overvoltage protection circuit just use the simple passive method, e.g. Transient voltage suppressor or zener diode, unlike a overcurrent case usually using an active protection method (desat protection with adjutable fault response time/blanking time). Therefore, I think the avalanche capability test cannot be used to guide our protection design.

2. The avalanche capability information given on device datasheet is based on the maximum junction temperature not exceeding 150 deg C. However, when a device is fail due to overvoltage, the actual junction temperature is much higher than 150 degC. So, I think the information on datasheet does not make any sense for a protection design.

Am I right?

Thanks so much for your comments and corrections.

Jack

 

[FvM]

I wonder which IGBT have a avalanche specification. Can you give an example?

Avalanche energy specifications are however common for power MOSFET.

2. The avalanche capability information given on device datasheet is based on the maximum junction temperature not exceeding 150 deg C. However, when a device is fail due to overvoltage, the actual junction temperature is much higher than 150 degC. So, I think the information on datasheet does not make any sense for a protection design.

Sounds confused. Permitted avalanche pulse energy is plotted versus (initial) junction temperature and approaches zero at tj,max. In other words, if you don't manage to keep the maximum junction temperature, your protection scheme is void.

The avalanche energy specification is important to determine if single ovevoltage events or periodical overvoltages (e.g. caused by parasitical circuit inductances) can be safely absorbed by a transistor. You'll notice that many switch mode applications are forcing the transistor periodically into avalanche mode, but usually with relatively small energy. If you can't keep avalanche operation within specified energy and temperature limits, catastrophic device failure is likely to happen.

 

[hndxwzq]

I wonder which IGBT have a avalanche specification. Can you give an example?

Avalanche energy specifications are however common for power MOSFET.


Sounds confused. Permitted avalanche pulse energy is plotted versus (initial) junction temperature and approaches zero at tj,max. In other words, if you don't manage to keep the maximum junction temperature, your protection scheme is void.

The avalanche energy specification is important to determine if single ovevoltage events or periodical overvoltages (e.g. caused by parasitical circuit inductances) can be safely absorbed by a transistor. You'll notice that many switch mode applications are forcing the transistor periodically into avalanche mode, but usually with relatively small energy. If you can't keep avalanche operation within specified energy and temperature limits, catastrophic device failure is likely to happen.

Thanks a lot for your comments! I have several comments on your response.

1. You are correct. It seems that avalanche capability is only for MOSFETs. I didn't found any IGBT datasheet with avalanche specification. Does it means that IGBT nearly have no avalanche capability?

2. The permitted avalanche pulse energy versus initial junction temperature is usually given in datasheet of MOSFETs based on the rated maximum junction temperature. However, right now I am trying to do the single-pulse destructive avalanche test to obtain the safe operating area (SOA) of a MOSFET. The junction temperature at the device failure time instant is much higher than rated junction temperature. How can I translate the destructive avalanche test results to guide my protection design? (I am asking this because in destructive short-circuit capability test, we can translate the short circuit withstanding time to design the fault response time of a overcurrent protection circuit)

3. One scenario for the single pulse avalanche condition is like this. When a MOSFET turns off a large short-circuit current by its overcurrent protection circuit, large voltage overshoot may be induced by the high di/dt and parasitic inductance. This voltage overshoot could damage the MOSFET if no soft turn-off or voltage clamping method is used. How do I know whether a MOSFET can turn off such a short circuit current successfully without being damaged by the overvoltage? Can I judge it based on the avalanche information given in datasheet?