Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

what's the Physical Design and Physical Verification

Status
Not open for further replies.

tybhsl

Member level 1
Joined
Dec 14, 2004
Messages
39
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
486
In ASIC Design ,what's the Physical Design and Physical Verification? Who can tell me and recommend some books for me? I just want to know the maim idear of the backend design for asic in more details. Thanks very much!
 

rprince006

Member level 4
Joined
Jul 16, 2004
Messages
79
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,286
Activity points
841
Physical design is refered to as the whole process from the netlist to GDSII, physical verification means the process of validation of the physical design, including DRC/ERC/LVS, and timing, signal integrity and power analysis etc.

You can find the latest pbulished books about physical design/verification by
searching on-line, using these key-words.
 

omid219

Advanced Member level 4
Joined
Feb 2, 2005
Messages
117
Helped
5
Reputation
10
Reaction score
1
Trophy points
1,298
Location
Malaysia
Activity points
988
Sherwani, N. "Algorithms for VLSI Physical Design Automation" is good book that
gives a good perspective on this topic. You can download it from EDA book section.
 

Raptor

Member level 2
Joined
Jul 6, 2001
Messages
49
Helped
7
Reputation
14
Reaction score
5
Trophy points
1,288
Activity points
369
Physical design refers to making layout for the design. This can include Full Custom (Layout for each transistor is made by hand) or semi-custom(Layout is automatically generated by a P&R tool from a netlist).

Physical Verification Refers to verifcation includes following two major two steps:
1.Design Rule Check
2. Layout for Schematic

1. DRC checks for if layout complies with Foundry rules that is if the layout will be manufacturable. Typically this will have width check,density check, spacing checks etc.

2. LVS checks if the layout matches with the reference. In case of full-custom the reference is spice netlist which is verified for functionality before getting into layout.

In case of semi-custom reference will be gate-level verilog netlist.

Hope this clarifies.
 

au_sun

Full Member level 2
Joined
Aug 5, 2004
Messages
147
Helped
15
Reputation
30
Reaction score
4
Trophy points
1,298
Activity points
1,184
u can find the detailed infos about physical design in
ASIC -by Micheal J Sebastin SMITH
 

pinkesh2001

Junior Member level 2
Joined
Feb 9, 2005
Messages
21
Helped
4
Reputation
8
Reaction score
1
Trophy points
1,283
Activity points
200
Physical design refers to making layout for the design. This can include Full Custom (Layout for each transistor is made by hand) or semi-custom(Layout is automatically generated by a P&R tool from a netlist).

Physical Verification Refers to verifcation includes following two major two steps:
1.Design Rule Check
2. Layout for Schematic
3.Antenna Check
4.Electrical Rule Check.

More on this you can clear it reading ASIC by Sebastian Smith.

Bye

Pinkesh
 
Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top