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What's the methodology to make a FIRST synthesis without WLM?

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ivlsi

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Hi All,

What's the methodology to make a FIRST synthesis without WLM (after this first run, the netlist will be passed to P&R for creation a Custom WLM)?

Should the clock frequency and in/out inputs be over-constrained? How much?

Thank you!
 

englishdogg

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Re: Synthesis without WLM

dmitryl

Have to say your curiosity with WLM is interesting :)

Now again to me this question has a lot of answer - many do it just to get the gate count / area or to create a first pass floorplan.
To create a custom WLM i dont see it ncessary to have it synthesized without WLM or also called as ZWLM (Zero Wire-Load Model)

Now to have a ZWLM netlist all you ahve to do is tell the tool not to use the WLM.
Hope i was able to answer your question
 

dftrtl

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Re: Synthesis without WLM

Generally at synthesis level we need to over constraint by 20%
 

englishdogg

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Re: Synthesis without WLM

that is fine... which is a standard practise across
Also the over constraint you mention i believe are 20% of theclock period right.. if yes then it is a fair number
 

dftrtl

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Re: Synthesis without WLM

This is the standard practise.
Yeah Shrink clock period by 20%
 

ivlsi

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Now to have a ZWLM netlist all you have to do is tell the tool not to use the WLM.
What command should be used for that?

- - - Updated - - -

Does the Custom WLM mean a back-annotation for a given design?
 

englishdogg

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In CDN RTl Compiler use the below
--
set_attr wireload_mode top /
set_attr wireload_selection none /
set_attr force_wireload none /des*/*
set_attr force_wireload none [find / -subdesign * ]
--

Custom WLM model is more of a way in which the exact net lengths are calculated since they are routed. But once this is applied on the RTL design this C-WLM is no more valid since the design has changed since then
 

vcnvcc

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I have gone through this thread, but still I have same question which has been asked.

Let me put it in simpler way
1. So when I start synthesizing my design 1st time, and at that time I wanted to use 'Zero WLM', then from where do I get it?
- I'll get it from library Vendor? OR
- I have to used existing WLM & in DC I have to provide some option saying used Zero dealy from WLM?

Can you please clarify?
 

englishdogg

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ZWLM as the name suggest is ZERO meaning no modelling to be applied i.e. no parasitics to be calculated.

Where there is nothing to calculate you dont need anything or provide anything. WLM are basically there in the lib provided by foundry and there are some which have a default assigned in the lib. So when you synthesize using a lib the default WLM in the lib gets applied to the design - is is here that you have to tell the tool RC / DC not to use the WLM and go for ZWLM.

Hope this clarifies.
 

vcnvcc

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Thanks for reply englishdogg

So all I have understood is -
step 1. While doing first synthesis - don't use WLM - the process of not using WLM in DC is called "used ZWLM"
Step 2. After that on next synthesis run, PnR team will deliver first real WLM, and that I have to use in Synthesis.

Please calrify - Now that WLM is final, I dont have to change after that - in any further run of Synthesis

Thanks,
 

englishdogg

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completely mis-understood.
Lets get more basic understanding -

WLM - which is available in library provided by foundry
ZWLM - means nothing is required from anywhere - just need to instruct the tool to not use any wireload
C-WLM - custom wireload is generated post pnr and re-applied during syntehsis for better modeling of parasitics

Now depending on the flow/requirements users may choose any of the above methodology to synthesize the design. Many go for physical synthesis as well - replacing wireload completely for better modelling

If the steps you questioned out first were more from the synthesis flow then that is also wrong - these are just inputs on how you wish to perform / execute your synthesis.
 
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