what's the meaning of "set_output_delay -min -1.0 ...&q

[gong.kidd]

set_output_delay

Hi guys,
I can't catch the meaning of negative values for the minimum value of output delay. Can somebody tell me? Thanks

 

[satya_422]

set_output_delay min

Assume that same like that when input hold(external) becomes -ve due to the data delays and Skew..

It mean that its reaching output early w.r.t. our timing analysis not in terms of time.

 

[satya_422]

set_output_delay -min

For more clarification Read this

The data setup time is the time the data inputs must be valid before the clock/strobe signal occurs. The hold time is the time the data must remain valid after the clock/strobe. Both can be zero or negative. An example is that t_SHDI - the data hold time after DS* is high is 0. A zero setup time means that the time for the data to propagate within the component and load into the latch is less than the time for the clock to propagate and trigger the latch. A zero hold time means either that the moment the clock is asserted, the latch no longer looks at its inputs, or else that the clock path delay is shorter than the data path delay. A negative setup or hold time means that there is an even larger difference in path delays, so that even if the data is sent later than the clock (for setup time), it still arrives at the latch first. Typically manufacturers avoid specifying negative values since this restricts later design and manufacturing decisions, but they often specify zero values since this simplifies usage in a system.


---satya

 

[floatgrass]

set_output_delay example

set_output_delay -min
-min= Thold -Tc
Thlod is the hold time of flip-flop. Tc is output of chip minimum path delay.

 

[spauls]

set_output_delay min max

This mean you are telling STA engine to perform hold analysis one edge before actual.

 

[funzero]

set_output_delay min negative

In my opnion , the output signal may trigger by more than one signal , we asume 2, the 2 signal may not change at same time . think these two condition considering this logic relation out = A &B; when that A hold its value and B change lead to a change in output signal the tranportation time is Tb , when B hold its value and A change , which result an time Ta , you can set_output_delay -min min{Ta , Tb} -max max{Ta, Tb}