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I have run designs with the fastest speed grades at about 260 MHz. You may be able to squeeze more out of these chips. The speed can be affected by your design, routing, and placement.
1. Depends on the speedgrade you select,
2. Depends on your design. More of combination logic in your design, lesser will be the acheivable frequency.
3. Depends on how big your design will be. If you are occupying more than 90% of the logic inside the FPGA, frequency will reduce noticeably.
4. Depends on your placement.
5. Depends on what kind of constraints you apply.
6. Depends on what kid of optimisation you choose.. area or speed
My experience has been that you can design large and complex designs to run around 200MHz if you are very careful with pipelining and so on. You can certainly push beyond this to the 300MHz mark for simple circuits but you don't get more than a layer or two of combinatorial logic at these speeds, thus restricting what you can do...
The next xilinx family (Virtex4 - not sure what happened to Virtex3) will be made on .75um process, which is significantly smaller than the 1.3um process used for Virtex2/Virtex2pro, so I imagine that you'll be able to sail right through the 300-400MHz barrier when these devices become available...
does any one have any such comments for spartan-3 fpgas? I have a design which I want to run at 100 Mhz. I just want to know how is the maximum frequency constrained by the technology.
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