Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

what's the matter in file test.v ?

Status
Not open for further replies.

quan228228

Full Member level 4
Joined
Mar 23, 2006
Messages
196
Helped
16
Reputation
32
Reaction score
3
Trophy points
1,298
Activity points
2,571
attempting to place a value change callback

Today i write a simple module "test.v" with verilog. when i run simulation with ncverilog, it can't dump fsdb file. why?

The following are test.v and .log file.
1) test.v
module test();
reg clock, reset;
wire out1;

initial begin
clock =0;
reset = 1;
#2990;
reset = 0;
end

always #100 clock = !clock;

test1 test1 (
.clk (clock),
.rst (reset),
.out (out1)
);


initial begin
$fsdbDumpfile ("test_bench.fsdb");
$fsdbDumpvars (test);

end

endmodule


module test1 (
clk,
out,
rst
);

input clk;
input rst;
output out;

reg out;

always @(posedge rst or posedge clk)
begin
if (rst)
out <= 1'b0;
else
out <= #3 1'b0;
end

endmodule

2) log file
ncverilog: 05.10-p004: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
TOOL: ncverilog 05.10-p004: Started on Oct 19, 2006 at 09:30:48
ncverilog
test.v
-l
ncverilog.log
Recompiling... reason: file './test.v' is newer than expected.
expected: Thu Oct 19 09:29:54 2006
actual: Thu Oct 19 09:30:42 2006
file: test.v
module worklib.test:v
errors: 0, warnings: 0
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.test:v <0x0e726cc3>
streams: 2, words: 678
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 2 2
Registers: 3 3
Scalar wires: 2 -
Always blocks: 2 2
Initial blocks: 2 2
Writing initial simulation snapshot: worklib.test:v
Loading snapshot worklib.test:v .................... Done
ncsim> source /usr/tools/cadence/ldv/tools/inca/files/ncsimrc
ncsim> run
Debussy Release 5.2v13 (Linux) NC-Verilog - 09/24/2002 compile
FSDB file test_bench.fsdb is created
Start dumping scope test, layer 0
ERROR: ACC VISNOC
Attempting to place a value change callback on test.out1 which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOC
Attempting to place a value change callback on test.clock which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOC
Attempting to place a value change callback on test.reset which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOC
Attempting to place a value change callback on test.test1.clk which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOC
Attempting to place a value change callback on test.test1.rst which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOC
Attempting to place a value change callback on test.test1.out which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.out1 which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.out1 which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.out1 which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.clock which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.clock which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.clock which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.reset which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.reset which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.reset which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.test1.clk which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.test1.clk which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.test1.clk which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.test1.out which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.test1.out which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.test1.out which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.test1.rst which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.test1.rst which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
ERROR: ACC VISNOR
Attempting to read from test.test1.rst which does not have read access.
./test.v, 31: $fsdbDumpvars(test)
End of dumping
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
TOOL: ncverilog 05.10-p004: Exiting on Oct 19, 2006 at 09:30:48 (total: 00:00:00)

Thanks for you take time to read and reply.

David
 

no_mad

Full Member level 5
Joined
Dec 10, 2004
Messages
272
Helped
30
Reputation
60
Reaction score
11
Trophy points
1,298
Location
Naboo
Activity points
2,408
attempting to place a value change callback on

hi quan228228,

I faced the same problem before with ncverilog. Please try the command below:

ncverilog test.v test1.v +ncelabargs+"-access +r" |run.log

Hope it helps,
-no_mad
 

    quan228228

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top