What's the equivalent in Verilog to defining set of registers in VHDL?

[vinod_g]

hai
In the VHDL if to have a set of registers we have to define as
reg[2:0][12:0] (as multi dimensional arrays.
here i can refer as reg[2]...............
what is equivalence code in the verilog
i wrote as [15:0]data[2:0].......... can i write as data[5] to refer data register

 

[shiv_emf]

basic verilog QUES.

Hey [15:0]data[2:0] ..
this code in verilog refers to 3 registers of width 16bits ...
data[5] is illegal as there is no 6th register !!
in general data[address] , this is used to access data memory !

 

[xuanzhu]

basic verilog QUES.

in verilog you can define a register variable lick reg [2:0] temp, and use this variable to iterate the arrays, for example
for(integer i = 0;i < array.size;i++)
begin
temp = reg;
if(temp == xxx)
begin
//use temp value
yyy;
end
end

 

[vinod_g]

Re: basic verilog QUES.

hai all
thanks for reply
for example if I define a register of [7] memory[2] means a an 8 bit memory with memory[0],meory[2]......to memory[7] .Now if I assign as
memory[0] <= data_in ,Now here my doubt is whether data_in is stored in the memory of LSB bit(only) or in the memory[0] named register. In the vhdl we can easily differntiate with named and bit vector register , but how in the case of verilog

Added after 3 minutes:

Hey [15:0]data[2:0] ..
this code in verilog refers to 3 registers of width 16bits ...
data[5] is illegal as there is no 6th register !!
in general data[address] , this is used to access data memory !

hi shiv_emf
can u explain detail .....
here data[2:0] means it is of array of 8 .AM i correct on this . means data[0].... .. ............data[7]

 

[echo47]

Re: basic verilog QUES.

The declaration "reg [7] memory [2]" would be a syntax error because you haven't specified the ranges.

"reg [7:0] memory [0:2]" declares three registers (numbered 0 through 2) each containing eight bits (numbered 7 through 0).
After doing that,
"memory[2]" refers to all eight bits of register 2.
"memory[2][5]" refers to bit 5 of register 2.
"memory[1][6:2]" refers to bits 6 through 2 of register 1.

 

[VLSI Banker]

Re: basic verilog QUES.

Declaration of an array in Verilog is:

reg [ v-1 : 0] arr [ a-1 : 0]

where v is the length of the vector we need.
a is the no. of locations, each of width 'v' .

Now,
1)

reg [1:0] vec ; means 'vec' is a vector of 2 bit wide
or
memory with one location 2 bit wide.

2)

reg [1:0] arr [2:0] ; means 'arr' is a memory with 3 locations (2 downto 0),
each of width 2.

 

[yasser_shoukry]

basic verilog QUES.

Sorry but your question is vague somehow, can you send the verilog code so we can answer your question?

Regards,
Yasser

 

[samuraign]

Re: basic verilog QUES.

hello Vinod_g,
if u question is
reg [6:0] mem[0:1];

then two memories of 7bit are there,
when u assign mem[0] = data_in
I think data_in is a 7bit stored in mem[0];

 

[shiv_emf]

basic verilog QUES.

hey i hope its clear now ...

reg data[2:0]
this means data is having 3 registers each of 1 bit !!

 

[dsairajkiran]

Re: basic verilog QUES.

thank you