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That sounds like a Xilinx FPGA question. Those confusing terms, especially "CLB", have various meanings depending on which FPGA family you are referring to. It's best to search for definitions in the data sheet of the particular FPGA family. For example, here are some words from the Spartan-3E data sheet:
The combination of a LUT and a storage element is known as a “Logic Cell”.
The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as combinatorial circuits. Each CLB contains four slices, and each slice contains two Look-Up Tables (LUTs) to implement logic and two dedicated storage elements that can be used as flip-flops or latches.
However, the CLB is arranged differently in, say, a Virtex-5.
The term "logic cell" is more often used in Xilinx CPLDs than Xilinx FPGAs.
Actually "logic cells" are specified in most Xilinx FPGA spec sheets as "equivalent logic elements/logic cells" which as echo47 mentioned is like the smallest logical unit of a FPGA/PLD. You can safely compare logic elements in altera devices to equivalent logic cells in Xilinx devices.
Virtex-5 has 4 LE's/Slice.Stratix III uses ALM (Adaptive Logic Modules) which are similar to Virtex-5 but Altera claims they have higher density. Overall it can be very confusing until you know the underlying architecture of elements. Hope I didn't confuse you further.
Yes. For example, in a Spartan-3E:
Each CLB contains four slices.
Each slice contains two logic cells.
Each logic cell contains one LUT and one D-flop.
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