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physical compiler is for obtaining a tighter integration between the logic synthesis which use wireload models ,which are inaccurate for DSM,and the following phase of placement and routing.
PC is different from DC for its physical synthesis, which means PC can do sythesis with the layout information of design, so the result of PC will have more high relationship with the result after layout, comparing the result of DC
Added after 3 minutes:
hi, amarnath
now some logic synthesis tools do not use wireload models anymore, in the new version DC 2005, wireload models will not use.
amarnath said:
physical compiler is for obtaining a tighter integration between the logic synthesis which use wireload models ,which are inaccurate for DSM,and the following phase of placement and routing.
the difference is runing DC before floorplan ,running PC, however, after floorplan.
DC employ wire load model and PC uses def file generated by floorplan and global routing infomation. so net delay calculated by PC is better than DC. DC is used for logic, PC is used for placement.
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