tianxialzg
Newbie level 3

some technology foundry provide compiler for register file.
but in verilog , register vector also can finish the same function, such as reg [7:0]a[0:128].
what's the advantage of the register file?
but in verilog , register vector also can finish the same function, such as reg [7:0]a[0:128].
what's the advantage of the register file?