Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

what's the difference between the two xilinx constraints

Status
Not open for further replies.

spriteice

Junior Member level 2
Joined
Sep 1, 2004
Messages
24
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
247
offset = after valid xilinx

"OFFSET IN BEFORE" and "OFFSET IN AFTER"

Are they functioning exactly the same?
 

xilinx offset in before

**broken link removed**



BEFORE defines the relationship between data arrival and the next clock edge. For example, OFFSET IN BEFORE indicates that data will be valid at the input pin of a Xilinx device at a specified time before the next clockedge arrives at the Xilinx device.

AFTER defines the relationship between data arrival and the current clock edge. For example, OFFSET IN AFTER indicates that data will be valid at the input of a Xilinx device at a specified amount of time AFTER the current clock edge on the upstream device.
 

so can i say actually they have the same function?

for example: assume the period is 30 ns

the following two constraints actually give the same OFFSET constraint.

OFFSET=IN 20.0 BEFORE "CLK"
OFFSET=IN 10.0 after BEFORE "CLK"

am I right?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top