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Link Library is related to the package given with Synopsys design compiler and target library is where u declare which tech that u would be using like 90nm r 65nm .. u should be having a pakage prvided by soem vendors ..
this snap is taken from the book.. advanced chip synthesys.. bhatnagar... chapter 3 pgno...77
You can download this book form edaupload/downoad forum... serach for bhatnagar......
Here what he explains......
""At this time, it is worth explaining the difference between the target_library
and the link_library system variables. The target_library specifies the name
of the technology library that corresponds to the library whose cells the
designers want DC to infer and finally map to. The link_library defines the
name of the library that refers to the library of cells used solely for reference,
i.e., cells in the link_library are not inferred by DC. For example, you may
specify a standard cell technology library as the target_library, while
specifying the pad technology library name and all other macros (RAMs,
ROMs etc.) in the link_library list. This means that the user would synthesize
the design that targets the cells present in the standard cell library, while
linking to the pads and macros that are instantiated in the design.
If the pad library is included in the target_library list, then DC may use the pads to
synthesize the core logic.
The target library name should also be included in the link_library list, as
shown in Example 3.1. This is important while reading the gate-level netlist
in DC. DC will not be able to link to the mapped cells in the netlist, if the
target library name is not included in the link library list. For this case, DC
generates a warning stating that it was unable to resolve reference for the
cells present in the netlist.
The target_library and link_library system variables allow the designer to
better control the mapping of cells. These variables also provide a useful
means to re-map a gate-level netlist from one technology to the other. In this
case, the link_library may contain the old technology library name, while the
target_library may contain the new technology library. Re-mapping can be
performed by using the translate command in dc_shell.""
This article is from solvnet copying it from you, i find interesting that simple questions can be searched easily in solvnet with one keyword :idea:
next time you have any questions search it once you will surely find answers
The target_library variable specifies the library that Design Compiler
uses to select cells for optimization and re-mapping. It is typically set
to only the standard cells library.
The link_library variable specifies every library that has cells referenced
by the netlist. The tool uses the libraries specified in the link_library
variable for resolving references (linking). The link_library can include
memory (RAM, ROM or any macro) libraries, in addition to the standard cell
library. For example,
set synthetic_library "dw_foundation.sldb"
set target_library "gates.db"
set link_library "* $synthetic_library $target_library io.db rams.db"
The "*" stands for all designs that have already been loaded into
Design Compiler. The synthetic_library variable specifies the
DesignWare library, which contains more complex cells.
The input design files for Design Compiler are often written using a
hardware description language (HDL) such as Verilog or VHDL.
Design Compiler uses technology libraries, synthetic or DesignWare
libraries during the synthesis process.
During the synthesis process, Design Compiler translates the HDL
description to components extracted from the generic technology
(GTECH) library and DesignWare library. The GTECH library consists
of basic logic gates and flip-flops. The DesignWare library contains
more complex cells such as adders and comparators. Both the GTECH and
DesignWare libraries are technology independent, that is, they are not
mapped to a specific technology library.
After translating the HDL description to gates, Design Compiler
optimizes and maps the design to a specific technology library,
known as the target library. The process is constraint driven.
Constraints are the designer's specification of timing and
environmental restrictions under which synthesis is to be performed.
Design Compiler uses the link library to resolve references. For a
design to be complete, it must connect to all the library components
and designs it references. This process is called linking the design or
Because, they are not optimized (nor inserted) by DesignCompiler. They are already exist in the input netlist (RTL or gate-level netlist). And they are not modified during synthesis.
So, target_library - contains gates, that DC uses for mapping (re-targeting) gates from input netlist to output netlist.
link_library contains gates, that DC may find in the input netlist. All of these gates (except RAM/ROM or other black-boxes (cells with unknown for DC functionality) will be mapped (translated) to the cells from target_library. If you input RTL does not contains any gates (contains only standard HDL statements) - you do not need link_library.